WM8961 datasheet(20/116 Pages) WOLFSON

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WM8961

Pre-Production

PP, August 2009, Rev 3.1

CONTROL INTERFACE

The WM8961 is controlled by writing to registers through a 2-wire serial control interface. A control

word consists of 24 bits. The first 8 bits (B23 to B16) are address bits that select which control register

is accessed. The remaining 16 bits (B15 to B0) are data bits, corresponding to the 16 bits in each

control register. Many devices can be controlled by the same bus, and each device has a unique 7-bit

address (this is not the same as the 8-bit address of each register in the WM8961). The default device

address is 1001010x (0x94h).

The WM8961 operates as a slave device only. The controller indicates the start of data transfer with a

high to low transition on SDIN while SCLK remains high. This indicates that a device address and

data will follow. All devices on the 2-wire bus respond to the start condition and shift in the next eight

bits on SDIN (7-bit address + Read/Write bit, MSB first). If the device address received matches the

address of the WM8961, then the WM8961 responds by pulling SDIN low on the next clock pulse

(ACK). If the address is not recognised or the R/W bit is ‘1’ when operating in write only mode, the

WM8961 returns to the idle condition and wait for a new start condition and valid address.

By default, the WM8961 control interface requires an MCLK to be present before register writes are

supported. To access the control interface without an MCLK, the user must set R8 (08h) Clocking2 bit

5 (CLK_SYS_ENA) =0. MCLK is not required to write to CLK_SYS_ENA.

Without MCLK, and with CLK_SYS_ENA=0, all registers can be updated and will maintain their

settings, however any changes to functionality of the write sequencer, headphone PGAs, and

headphone output stage will not take effect until MCLK is present. Enabling MCLK after the register

writes to enable the headphone PGA and headphone output stage may produce audible pops and

clicks, hence is not recommended.

The WM8961 supports several kinds of read and write operations, which are:

•

Single write

•

Single read

•

Multiple write using auto-increment

•

Multiple read using auto-increment

Auto-increment is enabled by default and can be disabled using the AUTO_INC bit as detailed in

Table 3.

These modes are shown in the section below. Terminology used in the following figures is as follows:

TERMINOLOGY

DESCRIPTION

Start Condition

Repeated start

Acknowledge

Stop Condition

ReadNotWrite

0 = Write

1 = Read

Table 2 Terminology

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