WM8961 datasheet(57/116 Pages) WOLFSON

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WM8961

Pre-Production

PP, August 2009, Rev 3.1

The Charge Pump can also be enabled by running the default Start-Up sequence as described in the

“Control Write Sequencer” section. (Similarly, it will be disabled by running the Shut-Down sequence.)

In these cases, the user does not need to write to the CP_ENA bit.

CHARGE PUMP CLOCKING

The charge pump clock is derived from SYSCLK, using a clock divider to generate a nominal 1MHz

clock, as shown in Figure 43. The exact frequency depends on MCLK and the charge pump clock

division ratio, which is based on the SAMPLE_RATE[2:0] and CLK_SYS_RATE[3:0] register settings.

For example, with MCLKDIV=0, SAMPLE_RATE[2:0]=000:

256fs: CLK_SYS_RATE[3:0]=0011 gives a charge pump clock division ratio of 12, hence

•

MCLK=12.288MHz gives a charge pump frequency of 1.024MHz at full output power.

•

MCLK=11.2896MHz gives a charge pump frequency of 940.8kHz at full output power.

128fs: CLK_SYS_RATE[3:0]=0001 gives a charge pump clock division ratio of 6, hence

•

MCLK=6.144MHz gives a charge pump frequency of 1.024MHz at full output power.

•

MCLK=5.6448MHz gives a charge pump frequency of 940.8kHz at full output power.

CHARGE PUMP CONTROL

In order to minimise power consumption, both the output voltages (VPOS and VNEG) and the

switching frequency of the charge pump are automatically adjusted according to the operating

conditions. This can take two forms:

Charge pump settings only depend on volume register settings (

CP_DYN_PWR[1:0] = 0b00): the maximum of LOUT1VOL and ROUT1VOL volume

mode of operation.

Dynamic (Class W) power saving: Charge pump settings depend on dynamic signal level

(CP_DYN_PWR[1:0] = 0b11) and volume register settings: the audio signal input to the DAC,

multiplied by the maximum of LOUT1VOL and ROUT1VOL volume register settings, is used

to control the charge pump mode of operation. This is the Wolfson ‘Class W’ mode, which

allows the power consumption to be optimised in real time.

The Charge Pump operating mode defaults to Register control. Dynamic (Class W) power saving may

be selected by setting the CP_DYN_PWR[1:0] bits to 0b11. If dynamic power saving is to be selected,

this register write must take place before the charge pump is enabled. If the write sequencer is used

to configure the DAC to HP path, this register write must take place before the write sequencer is

enabled and triggered. Dynamic power saving results in a very slight reduction in headphone driver

performance.

When the ADC sidetone is used for the headphone output, and the charge pump settings depend on

dynamic signal level CP_DYN_PWR[1:0] = 0b11), the charge pump will monitor the DAC output level

rather than the ADC sidetone level. If the ADC sidetone signal is likely to exceed the DAC output

level, to avoid clipping it is recommended to set the charge pump settings to depend on volume

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R82 (52h)

Charge

Pump B

1:0

CP_DYN_PWR[1:0]

Enable dynamic (Class W) power

saving

00: dynamic power saving

disabled

01: Reserved

10: Reserved

11: dynamic power saving

enabled

Table 42 Charge Pump Configuration Registers

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