WM8961 datasheet(71/116 Pages) WOLFSON

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WM8961

Pre-Production

PP, August 2009, Rev 3.1

CLOCKING AND SAMPLE RATES

Clocks for the ADC and DAC, DSP core functions, the digital audio interface (AIF), the charge pump

and the class D outputs are all derived from the MCLK clock input. This is as show in Figure 43.

MCLK

SYSCLK

DAC

MASTER

MODE

CLOCK

OUTPUTS

LRC

BCLK

f/N

f/2 (*)

ADC

f/N

Class D Switching Clock

SYSCLK

All internal clocks are derived from SYSCLK.

SYSCLK is either MCLK or MCLK/2

ADCDIV

DACDIV

BCLKDIV

BCLK rate is set by BCLKDIV in master mode.

Note that both ADC and DAC operate at the same

sample rate.

DCLKDIV

Class D switching clock frequency is set by DCLKDIV and should be set to

operate the Class D function at a frequency of

384 kHz for optimum performance

TIMEOUT

A slow clock is used for volume update timeouts (when zero cross is enabled).

The timeout period is set by CLK_TO_DIV

Other Sample Rate Controls

R4[2], MCLKDIV

R8[5], CLK_SYS_ENA

R56[8:5],

CLK_DCS_DIV[3:0]

f/N

DC Servo

R8[8:6],

DCLKDIV[2:0]

R8[3:0],

BCLKDIV[3:0]

R7[6], MS

R30[6:1],

CLK_256K_DIV[5:0]

TIMEOUT

R23[0], TOEN

R30[8,7],

CLK_TO_DIV[3:0]

Analog

Volume

Update

CLK_DCS_DIV

The DC Servo Clock is controlled by the CLK_DCS_DIV. This should be set to

provide a 1.5 MHz clock to the DC Servo.

ADC clock is set by ADCDIV (Master or Slave mode)

This is configured to output a clock of 256fs

DAC clock is set by DACDIV (Master or Slave mode)

This is configured to output a clock as close as possible to 3MHz

R4[8:6],

ADCDIV[2:0]

R4[5:3],

DACDIV[2:0]

SAMPLE_RATE[2:0] configures the ALC for a chosen sample rate.

DEEMPH[1:0] configures the de-emphasis filter for the chosen sample rate.

CLK_SYS_RATE[3:0] defines the relationship between the MCLK and the

sample rate

f/64

Charge

Pump

f/2

f/16

Write

Sequencer

f N

R14[8:0],

LRCLK_RATE[8:0]

R8[4],

CLK_DSP_ENA

LRCLK_RATE

LRC is set by the LRCLK_RATE in master mode.

This is an integer division of the BCLK.

CLK_256K_DIV

This is a general clock divider which divides down the

SYSCLK (default is SYSCLK/48 = 256 kHz when

SYSCLK =12.288MHz operation)

256fs(*)

R23[5],

ADC_OSR

4 kHz

Charge pump

clock division

f/N

(*) In 384fs mode, ADCDIV should be

configured to give 384fs. This is then

divided by f/3 to give 128fs for the ADC

Figure 43 Clock Structure

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