WM8961 datasheet(51/116 Pages) WOLFSON

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WM8961

Pre-Production

PP, August 2009, Rev 3.1

If the speakers are located close to the WM8961 (less than about 100mm) then the internal filtering

effects of the speaker can be used. Where speakers are located further away from the WM8961 and

the speaker signals are routed over longer distances, it is recommended to use additional passive

filtering. This additional filtering should be positioned as close as possible to the WM8961 to reduce

EMI effects. See “Applications Information” for more information on EMI reduction.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R8 (08h)

Clocking (2)

8:6

DCLKDIV[2:0]

111

Controls clock division from

SYSCLK to generate suitable class

D clock.

000 = SYSCLK / 1

001 = SYSCLK / 2

010 = SYSCLK / 3

011 = SYSCLK / 4

100 = SYSCLK / 6

101 = SYSCLK / 8

110 = SYSCLK / 12

111 = SYSCLK / 16

(Note that Class D function further

divides by 2 )

R49 (31h)

Class D

Control (1)

SPKR_ENA

Right channel class D enable

0= Disable Right Channel speaker

output

1= Enable Right Channel speaker

output

SPKL_ENA

Left channel Class D enable

0= Disable Left Channel speaker

output

1= Enable Left Channel speaker

output

Table 36 Class D Speaker Control Registers

INPUT AND OUTPUT VOLUME UPDATES

Volume settings will not be applied to input or output PGAs until a ‘1’ is written to one of the update

bits (IPVU, OUT1VU, SPKVU bits). This is to allow left and right channels to be updated at the same

time, as shown in Figure 23.

Figure 23 Simultaneous Left and Right Volume Updates

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