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WM8961 Scheda tecnica(PDF) 23 Page - Wolfson Microelectronics plc |
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WM8961 Scheda tecnica(HTML) 23 Page - Wolfson Microelectronics plc |
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23 / 116 page ![]() WM8961 Pre-Production w PP, August 2009, Rev 3.1 23 When the Automatic Level Control (ALC) is enabled the input PGA gains are controlled automatically and the LINVOL and RINVOL bits should not be used. The left and right input PGAs can be independently muted using the LINMUTE and RINMUTE register bits. To allow simultaneous volume updates of left and right channels, PGA gains are not altered until a 1 is written to the IPVU bit. To prevent "zipper noise", a zero-cross function is provided, so that when enabled, volume updates will not take place until a zero-crossing is detected. This can be enabled using the LIZC and LIZC register bits. These bits must be written as a separate register write, before the volume setting is applied. For example, to change the left and right volumes simultaneously, with zero cross enabled, the sequence would be as detailed in Table 5. It is recommended to perform a calibration of the DC Servo input channel before using the Input PGA Zero Cross Detector. REGISTER VALUE COMMENT R0 (00h) Left Channel PGA 0bxx1x_xxxx LIZC = 1: Enable Left Input PGA Zero Cross Detector R1 (01h) Right Channel PGA 0bxx1x_xxxx RIZC = 1: Enable Right Input PGA Zero Cross Detector R0 (00h) Left Channel PGA 0b001y_yyyy IPVU = 0; LINMUTE = 0; LIZC = 1; LINVOL [5:0] = 0by_yyyy: Apply Left Input PGA volume setting, keep Zero Cross enabled, store update. R1 (01h) Right Channel PGA 0b101y_yyyy IPVU = 1; RINMUTE = 0; RLIZC = 1; RINVOL [5:0] = 0by_yyyy: Apply Right Input PGA volume setting, keep Zero Cross enabled, update left and right channel gains simultaneously. Table 5 Simultaneous Volume update with Zero Cross In the event of a long period without zero-crossings, a timeout function is available. When this function is enabled (using the TOEN register bit), the volume will update automatically after a timeout. The timeout period is set by CLK_TO_DIV[2:0] Note that SYSCLK must be running to use this function. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R0 (00h) Left Channel PGA 8 IPVU 0 Input PGA Volume Update 0 = Store LINVOL in intermediate latch (no gain change) 1 = Update left and right channel gains (left = LINVOL, right = intermediate latch) 7 LINMUTE 1 Left Input PGA Analogue Mute 1 = Enable Mute 0 = Disable Mute Note: IPVU must be set to un- mute. 6 LIZC 0 Left Input PGA Zero Cross Detector. Requires separate register write before volume setting. 1 = Change gain on zero cross only 0 = Change gain immediately 5:0 LINVOL [5:0] 011111 ( 0dB ) Left Input PGA Volume Control 111111 = +24dB 111110 = +23.25dB . . 0.75dB steps down to 000000 = -23.25dB |
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