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WM8961 Scheda tecnica(PDF) 59 Page - Wolfson Microelectronics plc

Il numero della parte WM8961
Spiegazioni elettronici  Ultra-Low Power Stereo CODEC with 1W Stereo Class D Speaker Drivers and Ground Referenced Headphone Drivers
PDF  116 Pages
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Produttore elettronici  WOLFSON [Wolfson Microelectronics plc]
Homepage  http://www.wolfsonmicro.com
Logo WOLFSON - Wolfson Microelectronics plc

WM8961 Scheda tecnica(HTML) 59 Page - Wolfson Microelectronics plc

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WM8961
Pre-Production
w
PP, August 2009, Rev 3.1
59
MASTER MODE BCLK AND LRC GENERATION
The BCLK frequency is controlled by BCLKDIV[3:0] which must be set appropriately to support the
ADC and DAC sample rate.
The LRC is set by the LRCLK_RATE[ 8:0] which is an integer division of the BCLK.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R8 (08h)
Clocking2
3:0
BCLKDIV[3:0]
0100
BCLK Frequency (Master Mode)
0000 = SYSCLK
0001 = Reserved
0010 = SYSCLK / 2
0011 = SYSCLK / 3
0100 = SYSCLK / 4 (default)
0101 = Reserved
0110 = SYSCLK / 6
0111 = SYSCLK / 8
1000 = Reserved
1001 = SYSCLK / 12
1010 = SYSCLK / 16
1011 = SYSCLK / 24
1100 = Reserved
1101 to 1111 = SYSCLK / 32
R14 (0Eh) Audio
Interface 2
8:0
LRCLK_RATE[8:0]
0_0100_0000 Integer divide of BCLK. 50:50 LRCLK duty cycle is only
guaranteed with even values (4, 6, … … , 510).
0_0000_0000 to 0_0000_0011 : reserved
0_0000_0100 : 4
…
0_0100_0000 : 64
…
1_1111_1110 : 510
1_1111_1111: Reserved
Table 43 Master Mode BCLK and LRC Configuration
Internal clock divide and phase control mechanisms ensure that the BCLK and LRC edges will occur
in a predictable and repeatable position relative to each other and to the data.
See Clocking and Sample Rates section for more information.



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