TMS570LS datasheet(53/107 Pages) TI1

Il numero della parte	TMS570LS

Spiegazioni elettronici	Series 16/32-BIT RISC Flash Microcontroller

PDF	107 Pages

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Produttore elettronici	TI1 [Texas Instruments]

Homepage	http://www.ti.com

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CPU 1

CPU 2

1.5cycle delay

CCM-R4

CPU1CLK

CPU2CLK

Compare

Error

CCM-R4

Compare

TMS570LS20206-EP, TMS570LS20216-EP

www.ti.com

SPNS209A – JUNE 2012 – REVISED AUGUST 2012

4.9

CCM

4.9.1

Dual Core Implementation

The microcontroller has two Cortex-R4 cores, where the output signals of both CPUs are compared in the

CCM-R4 (Core Compare Module). To avoid common mode impacts the signals of the CPUs to be

compared are delayed in a different way as shown in the following figure.

Figure 4-2. Dual Core Implementation

4.9.2

CCM-R4

To avoid an erroneous CCM-R4 compare error, the application software must ensure that the CPU

registers of both CPUs are initialized with the same values before the 1st function call or other operation

that pushes the CPU registers onto the stack. All CCM-R4 error forcing test modes are limited to 100MHz

HCLK speed.

Peripherals

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Product Folder Link(s): TMS570LS20206-EP TMS570LS20216-EP

TMS570LS Scheda tecnica(PDF) 53 Page - Texas Instruments