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TMS570LS Scheda tecnica(PDF) 91 Page - Texas Instruments |
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TMS570LS Scheda tecnica(HTML) 91 Page - Texas Instruments |
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91 / 107 page ![]() t(ETM)cyc t(ETM)r t(ETM)f t(ETM)h t(ETM)l EMIFCS[3:0] EMIFBADD[1:0] EMIFADD[21:0] EMIFWE EMIFD[15:0] EMIFOE 12 1 13 15 17 19 18 16 14 21 20 TMS570LS20206-EP, TMS570LS20216-EP www.ti.com SPNS209A – JUNE 2012 – REVISED AUGUST 2012 7.14.2 Write Timing (Asynchronous RAM) Figure 7-18. Asynchronous Memory Write Timing for EMIF 7.15 ETM Timings 7.15.1 ETMTRACECLK Timing Figure 7-19. ETMTRACECLK Timing Table 7-20. ETMTRACECLK Timing Parameter Minimum Maximum Description f(ETM)cyc 40MHz Clock frequency t(ETM)cyc 25ns Clock period t(ETM)l 2ns Low pulse width t(ETM)h 2ns High pulse width t(ETM)r 3ns Clock and data rise time t(ETM)f 3ns Clock and data fall time Copyright © 2012, Texas Instruments Incorporated Peripheral and Electrical Specifications 91 Submit Documentation Feedback Product Folder Link(s): TMS570LS20206-EP TMS570LS20216-EP |
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