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TMS570LS Scheda tecnica(PDF) 79 Page - Texas Instruments |
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TMS570LS Scheda tecnica(HTML) 79 Page - Texas Instruments |
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79 / 107 page ![]() TMS570LS20206-EP, TMS570LS20216-EP www.ti.com SPNS209A – JUNE 2012 – REVISED AUGUST 2012 7.8 Flash Timings Table 7-12. Timing Requirements For Program Flash MIN NOM MAX Unit tprog(32-bit) Full word (32-bit) programming time 33 300 µs tprog(Total) 2M-byte programming -40°C to 125°C 17 74 s time(1) 0°C to 60°C, for first 25 17 25 s cycles tprog ECC(16-bit) ECC programming time 33 300 µs tprog ECC(total) Total ECC bit -40°C to 125°C 4.3 15 s programming time (256k- 0°C to 60°C, for first 25 4.3 7 s byte) cycles terase(sector) Sector erase time -40°C to 125°C 2 15 s (including compaction) 0°C to 60°C, for first 25 1.5 10 s cycles terase(bank) Bank erase time (including Bank 0 7.5 20 s compaction),0°C to 60°C, Bank 1 5.5 12 s for first 25 cycles Bank 2 5.5 12 s Bank 3 5.5 12 s twec Write/erase cycles at TA = -40 to 125°C (2) 1000 cycles tret Data Retention with continuous 150°C (2) 1000 hours (1) This programming time includes overhead of state machine, but does not include data transfer time. (2) Flash write/erase cycles and data retention specifications are based on a validated implementation of the TI flash API. Non-TI flash API implementation is not supported. For detailed description see the F035 Flash Validation Procedure (SPNA127). The flash memory cells are qualified for data retention greater than 1000 hours at 150°C. Data retention at reduced temperatures can be estimated based on an Arrhenius model with activation energy of 1 eV. Copyright © 2012, Texas Instruments Incorporated Peripheral and Electrical Specifications 79 Submit Documentation Feedback Product Folder Link(s): TMS570LS20206-EP TMS570LS20216-EP |
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