TMS570LS datasheet(84/107 Pages) TI1

84 / 107 page

TMS570LS20206-EP, TMS570LS20216-EP

SPNS209A – JUNE 2012 – REVISED AUGUST 2012

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7.10 SPI Slave Mode Timing Parameters

7.10.1 SPI Slave Mode External Timing Parameters (CLOCK PHASE = 0, SPICLK = input,

SPISIMO = input, and SPISOMI = output)

Table 7-15. SPI Slave Mode External Timing Parameters (1)(2)(3)

NO.

MIN

MAX

Unit

tc(SPC)S

Cycle time, SPICLK(4)

2(5)

tw(SPCH)S

Pulse duration, SPICLK high(clock polarity = 0)

tw(SPCL)S

Pulse duration, SPICLK low(clock polarity = 1)

3(5)

tw(SPCL)S

Pulse duration, SPICLK low(clock polarity = 0)

tw(SPCH)S

Pulse duration, SPICLK high(clock polarity = 1)

4(5)

td(SPCH-SOMI)S

Delay time, SPISOMI valid after SPICLK high

trf(SOMI) + 15

(clock polarity = 0)

td(SPCL-SOMI)S

Delay time, SPISOMI valid after SPICLK low (clock

trf(SOMI) + 15

polarity = 1)

5(5)

tV(SPCH-SOMI)S

Valid time, SPISOMI data valid after SPICLK high

(clock polarity =0)

tV(SPCL-SOMI)S

Valid time, SPISOMI data valid after SPICLK low

(clock polarity =1)

6(5)

tsu(SIMO-SPCL)S

Setup time, SPISIMO before SPICLK low(clock

polarity = 0)

tsu(SIMO-SPCH)S

Setup time, SPISIMO before SPICLK high(clock

polarity = 1)

7(5)

th(SPCL-SIMO)S

Hold time, SPISIMO data valid after SPICLK low

(clock polarity = 0)

th(SPCH-SIMO)S

Hold time, SPISIMO data valid after S PICLK high

(clock polarity = 1)

td(SPCL-SENAH)S

Delay time, SPIENAn high after last SPICLK low

1.5tc(VCLK)

2.5tc(VCLK)+tr(ENAn)+ 26

(clock polarity = 0)

td(SPCH-SENAH)S

Delay time, SPIENAn high after last SPICLK high

1.5tc(VCLK)

2.5tc(VCLK)+tr(ENAn)+ 26

(clock polarity = 1)

td(SCSL-SENAL)S

Delay time, SPIENAn low after SPICSn low (if new

tf(ENAn)

tc(VCLK) + tf(ENAn)+ 18

data has been written to the SPI buffer)

(1)

The MASTER bit (SPIGCR1.0) is set and the CLOCK PHASE bit (SPIFMTx.16) is set.

(2)

tc(VCLK) = interface clock cycle time = 1 /f(VCLK)

(3)

For rise and fall timings, see the "switching characteristics for output timings versus load capacitance" table.

(4)

When the SPI is in Slave mode, the following must be true:

tc(SPC)S > 2tc(VCLK) and tc(SPC)S>= 90 ns.

tw(SPCH)S > tc(VCLK) and tw(SPCL)S > tc(VCLK).

(5)

The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17).

Peripheral and Electrical Specifications

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