TMS570LS datasheet(82/107 Pages) TI1

82 / 107 page

TMS570LS20206-EP, TMS570LS20216-EP

SPNS209A – JUNE 2012 – REVISED AUGUST 2012

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7.9.2

SPI Master Mode External Timing Parameters (CLOCK PHASE = 1, SPICLK = output,

SPISIMO = output, and SPISOMI = input)

Table 7-14. SPI Master Mode External Timing Parameters(1)(2)(3)

NO.

MIN

MAX

Unit

tc(SPC)M

Cycle time, SPICLK (4)

256tc(VCLK)

2(5)

tw(SPCH)M

Pulse duration, SPICLK high (clock polarity = 0)

0.5tc(SPC)M – 3 – tr

0.5tc(SPC)M + 5

tw(SPCL)M

Pulse duration, SPICLK low (clock polarity = 1)

0.5tc(SPC)M – 3 – tf

0.5tc(SPC)M + 5

3(5)

tw(SPCL)M

Pulse duration, SPICLK low (clock polarity = 0)

0.5tc(SPC)M – 3 – tr

0.5tc(SPC)M + 5

tw(SPCH)M

Pulse duration, SPICLK high (clock polarity = 1)

0.5tc(SPC)M – 3 – tf

0.5tc(SPC)M + 5

4(5)

td(SIMO-SPCH)M

Delay time, SPICLK high after SPISIMO data

0.5tc(SPC)M – 10

valid(clock polarity = 0)

td(SIMO-SPCL)M

Delay time, SPICLK low after SPISIMO data valid

0.5tc(SPC)M – 10

(clock polarity = 1)

5(5)

tv(SPCH-SIMO)M

Valid time, SPISIMO data valid after SPICLK

0.5tc(SPC)M – tr(SPC) – 7

high(clock polarity = 0)

tv(SPCL-SIMO)M

Valid time, SPISIMO data valid after SPICLK

0.5tc(SPC)M – tf(SPC) – 7

low(clock polarity = 1)

6(5)

tsu(SOMI-SPCH)M

Setup time, SPISOMI before SPICLK high (clock

tr(SPC)+4

polarity = 0)

tsu(SOMI-SPCL)M

Setup time, SPISOMI before SPICLK low (clock

tf(SPC)

polarity = 1)

7(5)

tv(SPCH-SOMI)M

Valid time, SPISOMI data valid after SPICLK high

(clock polarity = 0)

tv(SPCL-SOMI)M

Valid time, SPISOMI data valid after SPICLK low

(clock polarity = 1)

8(6)

tC2TDELAY

Setup time CS active until SPICLK high, assumes

(C2TDELAY+CSHOLD+

that SPInENA is low at tSPIENA (clock polarity = 0)

2)*tc(VCLK) +0.5*tc(SPC)M - 2)*tc(VCLK) +0.5*tc(SPC)M -

tf(SPICS) + tr(SPC) - 9

tf(SPICS) + tr(SPC) + 5

Setup time CS active until SPICLK low, assumes

(C2TDELAY+CSHOLD+

that SPInENA is low at tSPIENA (clock polarity = 1)

2)*tc(VCLK) + 0.5*tc(SPC)M

- tf(SPICS) + tf(SPC) - 9

- tf(SPICS) + tf(SPC) + 5

9(6)

tT2CDELAY

Hold time SPICLK low until CS inactive (clock

T2CDELAY*tc(VCLK) +

polarity = 0)

tc(VCLK) - tf(SPC) + tr(SPICS) tc(VCLK) - tf(SPC) + tr(SPICS)

- 5

+ 10

Hold time SPICLK high until CS inactive (clock

T2CDELAY*tc(VCLK) +

polarity = 1)

tc(VCLK) - tr(SPC) +

tr(SPICS)- 5

tr(SPICS)+ 10

tSPIENA

SPIENAn Sample Point

C2TDELAY * tc(VCLK) -

C2TDELAY * tc(VCLK)

tf(SPICS)- 20

tSPIENAW

SPIENAn Sample point from write to buffer

(C2TDELAY+2)*tc(VCLK)

(1)

The MASTER bit (SPIGCR1.0) is set and the CLOCK PHASE bit (SPIFMTx.16) is set.

(2)

tc(VCLK) = interface clock cycle time = 1 / f(VCLK)

(3)

For rise and fall timings, see the "switching characteristics for output timings versus load capacitance" table.

(4)

When the SPI is in Master mode, the following must be true:

For PS values from 1 to 255: tc(SPC)M ≥ (PS +1)tc(VCLK) ≥ 50 ns, where PS is the prescale value set in the SPIFMTx.[15:8] register bits.

For PS values of 0: tc(SPC)M = 2tc(VCLK) ≥ 50 ns. The external load on the SPICLK pin must be less than 60pF.

(5)

The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17).

(6)

C2TDELAY and T2CDELAY are programmed in the SPIDELAY register

Peripheral and Electrical Specifications

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