ADSP-SC596 datasheet(112/134 Pages) AD

112 / 134 page

Rev. PrD

Page 112 of 134

May 2022

ADSP-SC595/SC596/SC598

Preliminary Technical Data

Table 76 and Figure 53 show the default I2S justified mode. The frame sync is low for the left channel and high for the right channel. Data

is valid on the rising edge of the serial clock. The MSB is left justified to the frame sync transition but with a delay.

Table 77 and Figure 54 show the left justified mode. The frame sync is high for the left channel and low for the right channel. Data is valid

on the rising edge of the serial clock. The MSB is left justified to the frame sync transition with no delay.

Table 76. S/PDIF Transmitter I2S Mode

All specifications are based on simulation data and are subject to change without notice.

Parameter

Nominal

Unit

Timing Requirement

tI2SD

Frame Sync to MSB Delay in I2S Mode

SCLK0

Figure 53. I2S Justified Mode

Table 77. S/PDIF Transmitter Left Justified Mode

All specifications are based on simulation data and are subject to change without notice.

Parameter

Nominal

Unit

Timing Requirement

tLJD

Frame Sync to MSB Delay in Left Justified Mode

SCLK0

Figure 54. Left Justified Mode

MSB

LEFT/RIGHT CHANNEL

LSB

MSB–1

MSB–2

LSB+2

LSB+1

DAI_P20–1

(FS)

DAI_P20–1

(SCLK0)

DAI_P20–1

(SDATA)

tI2SD

MSB

LEFT/RIGHT CHANNEL

LSB

MSB–1

MSB–2

LSB+2

LSB+1

DAI_P20–1

(FS)

DAI_P20–1

(SCLK0)

DAI_P20–1

(SDATA)

tLJD

ADSP-SC596 Scheda tecnica(PDF) 112 Page - Analog Devices

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