ADSP-SC596 datasheet(110/134 Pages) AD

Il numero della parte	ADSP-SC596

Spiegazioni elettronici	SHARC Dual-Core DSP with Arm Cortex-A55

PDF	134 Pages

Scroll/Zoom	100%

Produttore elettronici	AD [Analog Devices]

Homepage	http://www.analog.com

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110 / 134 page

Rev. PrD

Page 110 of 134

May 2022

ADSP-SC595/SC596/SC598

Preliminary Technical Data

Extended Mobile Storage Interface (eMSI) Controller Timing—eMMC DDR Mode

Table Table 74 and Figure 51 show I/O timing related to the eMSI with eMMC DDR mode.

Table 74. eMSI Controller Timing—eMMC DDR Mode1

1 Refer to Table 72 for tPP and parameters for command.

All specifications are based on simulation data and are subject to change without notice.

Parameter

Min

Max

Unit

Timing Requirements

tISUDDR

Input Data Setup Time

2.5

tIHDDR

Input Data Hold Time

Switching Characteristic

tODLYDDR

Output Data Delay

2.6

Figure 51. eMSI Controller Timing with eMMC DDR Mode

tIHDDR

DATA

tODLYDDR (MAX)

tPP

CLK

INPUT

DATA

tISUDDR

INVALID

DATA

tISUDDR

tIHDDR

tODLYDDR (MIN)

tODLYDDR (MAX)

OUTPUT

DATA

IN DRR MODE, DATA ON DAT[7:0] LINES ARE SAMPLED ON BOTH EDGES OF THE CLOCK

(NOT APPLICABLE FOR CMD LINE)

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