ADIN1101CCPZ-R7 datasheet(38/79 Pages) AD

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Data Sheet

ADIN1101

MDIO INTERFACE

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Rev. A | 38 of 79

The management interface provides a 2-wire serial interface

(MDIO) between a host controller (such as microcontroller or an

external MAC chip) and the ADIN1101, allowing read and write

operations in the management registers.

The management interface of the ADIN1101 is compatible with both

IEEE Standard 802.3 Clause 22 and IEEE Standard 802.3 Clause

45.

The hardware configuration pins determine the default value of

some registers after power-up, hardware reset, or software reset.

For those registers, the reset value referenced in the register bit

description tables is listed as pin dependent. This dependency

allows the ADIN1101 to be configured in hardware without the

need for software operations over the MDIO interface (unmanaged

application).

The Hardware Configuration Pins section provides full details on

configuration pin setup for managed and unmanaged applications.

The access permissions of the registers are as follows:

►

R/W: read/write

►

R: read only

►

R LL: read only, latch low

►

R LH: read only, latch high

►

R/W SC: read/write, self clear

►

R SC: read only, self clear

CLAUSE 22

IEEE Standard 802.3 Clause 22 allows access to up to 32 registers

in 32 different PHY addresses.

The IEEE Clause 22 MDIO manageable device (MMD) register

access format is shown in Table 35 and Table 36.

Table 35. Clause 22 Frame Format

MSB

LSB

D31 to D30

D29 to D28

D27 to D23

D22 to D18

D17 to D16

D15 to D0

PHYADR

REGAD

Data

Table 36. Clause 22 Input Register Decode

Bit

Description

2-bit start of frame (01 for Clause 22)

2-bit operation code

01: write

10: read

PHYADR

5-bit PHY address

REGAD

5-bit register address

2-bit turn around field used to avoid contention during a read transition, 2-bit time spacing between register address field and data field

Data

16-bit data, MSB first

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