ADIN1101CCPZ-R7 datasheet(17/79 Pages) AD

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Data Sheet

ADIN1101

THEORY OF OPERATION

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Link status change interrupt

Those conditions can be set to enable an interrupt on the INT

pin using PHY_SUBSYS_IRQ_MASK (see the PHY Subsystem

Interrupt Mask Register section).

Following a hardware interrupt on the INT pin, the interrupt source

can be checked using PHY_SUBSYS_IRQ_STATUS (see the PHY

Subsystem Interrupt Status Register section).

Hardware Reset Interrupt

The ADIN1101 can also be configured to generate a hardware in-

terrupt after a hardware reset (RESET pin pulled low) by setting the

enable hardware reset interrupt bit (CRSM_HRD_RST_IRQ_EN)

in CRSM_IRQ_MASK (see the System Interrupt Mask Register

section).

Following a hardware interrupt on the INT pin, the interrupt

source can be checked with the CRSM_HRD_RST_IRQ_LH bit

in CRSM_IRQ_STATUS (see the System Interrupt Status Register

section).

Software Requested Interrupt

For system validation with an external host controller, the ADIN1101

can be requested to generate a hardware interrupt on the INT pin

using the CRSM_SW_IRQ_REQ bit in CRSM_IRQ_MASK (see the

System Interrupt Mask Register section).

Following a hardware interrupt on the INT pin, the interrupt

source can be checked with the CRSM_SW_IRQ_LH bit in

CRSM_IRQ_STATUS (see the System Interrupt Status Register

section).

System Error Interrupts

The ADIN1101 can also generate system errors interrupts. The

interrupt flags are located within the reserved bit sections of

CRSM_IRQ_STATUS (see the System Interrupt Status Register

section).

CRSM_IRQ_MASK (see the System Interrupt Mask Register sec-

tion) must be configured to allow system error interrupts. Refer

to Table 98 for details on the interrupts mask. The ADIN1101

must be hardware reset to recover from a system error interrupt

(CRSM_IRQ_STATUS reserved bits read as 1).

RESET OPERATIONS

Overview

The ADIN1101 supports the following chip resets:

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Power-on reset

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Hardware reset

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Software reset

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MAC interface reset

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PHY subsystem reset

All of these resets put the ADIN1101, including the PHY core, into a

known state. Whenever the PHY core is reset, the ADIN1101 MAC

interface output pins are driven to a low state.

Power-On Reset

The ADIN1101 includes a power supply monitoring circuit to ensure

that the chip has the correct voltage supply before initiating the

power-up sequence. During power-up, the ADIN1101 is held in

hardware reset until each of the supplies has crossed its minimum

rising threshold value and the power is considered good.

Hardware Reset

A hardware reset is initiated by the power-on reset circuitry or

by asserting the RESET pin low for a minimum of 10 µs. The

ADIN1101 includes a deglitch circuitry on this pin to reject pulses

shorter than 1 µs.

When the RESET pin is deasserted, all the input/output (I/O) pins

are held in tristate mode, the hardware configuration pins are

latched, and the I/O pins are configured to their functional mode.

When all the external and internal supplies are valid and stable,

the crystal oscillator circuit is enabled. After the crystal has started

up and stabilized, the phase-locked loop (PLL) is enabled. After a

delay of 50 ms (maximum) from the deassertion of the RESET pin,

all the internal clocks are valid, the internal logic is released from

reset, and all the management interface registers are accessible

over the MDIO interface.

The CLK25_REF clock output stays low while the RESET pin is

asserted low and remains low for another 70 ms (maximum) after

the RESET pin is deasserted.

Software Reset

A full chip software reset is initiated by setting the software reset

bit (CRSM_SFT_RST). When this bit is set, the chip fully initializes,

almost equivalent to a hardware reset except that it does not go

through the voltage supply validation sequence. The I/O pins are

held in tristate mode, the hardware configuration pins are latched,

and then the I/O pins are configured to their functional mode.

The crystal oscillator circuit is enabled, and after the crystal has

started up and stabilized, the PLL is enabled. Approximately 10 ms

(maximum) after setting the CRSM_SFT_RST bit, the internal logic

is released from reset and all the management interface registers

are accessible. The system ready bit (CRSM_SYS_RDY) indicates

that the start-up sequence is complete and the system is ready for

normal operation.

The CLK25_REF clock output remains low for 25 ms (maximum)

following a software reset.

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