ADIN1101CCPZ-R7 datasheet(12/79 Pages) AD

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Data Sheet

ADIN1101

THEORY OF OPERATION

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Only configure the MAC interface to RMII in software when the

required 50 MHz clock is available. See the MAC Interface Configu-

ration Register section for more details on RMII parameters.

Figure 11. RMII MAC PHY Interface Signals

RGMII Mode

For the receive RGMII, the ADIN1101 generates a 2.5 MHz RXC

signal to synchronize RXD_3 to RXD_0. RX_CTL is a combination

of the RX_DV and RX_ER signals (as described in Table 8) using

both edges of the RXC signal. The ADIN1101 transmits the RX_DV

signal on the positive edge of RXC and a combination (XOR

function) of RX_DV and RX_ER on the negative edge of RXC.

For the transmit RGMII, the ADIN1101 generates a 2.5 MHz refer-

ence clock on TX_CLK. The MAC transmits the TXD_3 to TXD_0

data on both edges of TXC. TX_CTL is a combination of the TX_EN

and TX_ER (as defined in the IEEE 802.3 Standard) signals using

both edges of TXC. TX_EN is transmitted on the positive edge of

TXC, and a combination (XOR function) of TX_EN and TX_ER is

transmitted on the negative edge of TXC.

Figure 12. RGMII MAC PHY Interface Signals

TRANSMIT AMPLITUDE CONFIGURATION

The ADIN1101 supports two transmit amplitude modes of opera-

tion, as follows:

►

1.0 V p-p and 2.4 V p-p mode (high level)

►

1.0 V p-p only mode

The high level transmit operating mode allows the ADIN1101 to

support both voltage levels. The operating level can then be au-

tomatically configured during autonegotiation (if enabled) based

on the link partner capabilities. Note that the high level transmit

operating mode of 2.4 V p-p requires an AVDD_H supply voltage of

3.3 V. Otherwise, if the supply voltage is less than 3.3 V, the device

may not start up correctly.

The mode of operation is configured through the TX2P4_EN hard-

ware configuration pin signal (see the Transmit Amplitude section).

The ADIN1101 also configures the default value for the transmit

level register bits used for the autonegotiation process based on the

level configured with the RX_D0/ TX2P4_EN pin (see the Transmit

Amplitude Advertisement section).

The ADIN1101 is configured in high level transmit operating mode

by default if the RX_D0/TX2P4_EN pin is left floating (internal

pull-down resistor).

LEADER/FOLLOWER CONFIGURATION

The 10BASE-T1L standard uses a leader/follower clock scheme.

This scheme is commonly used in full duplex transceiver standards

with echo cancellation. One PHY is designated as the leader, and

the other PHY as the follower. Autonegotiation is used to determine

which PHY is the leader and which is the follower. leader and

follower assignment does not generally matter.

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