ADIN1101CCPZ-R7 datasheet(7/79 Pages) AD

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Data Sheet

ADIN1101

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

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Rev. A | 7 of 79

Figure 4. Pin Configuration

Table 8. Pin Function Descriptions

Pin No.

Mnemonic1

PU/PD2

Description

Clock Interface

CLK25_REF

N/A

Analog Reference Clock Output. The 25 MHz reference clock from the crystal

oscillator is available on the CLK25_REF pin. This pin can be used as an

input to another PHY. The 25 MHz clock output is briefly disabled (logic low)

following a software reset (25 ms) or a hardware reset (70 ms). See the Reset

Operations section for more details.

XTAL_I/CLK_IN

N/A

Input for Crystal (XTAL_I).

Single-Ended 25 MHz Reference Clock or 50 MHz Clock Input for RMII

(CLK_IN).

XTAL_O

N/A

Crystal Output. If using a single-ended reference clock on XTAL_I/CLK_IN,

leave XTAL_O open circuit. See the External 25 MHz Clock Input for MII and

RGMII Modes section.

Management Interface

INT

Management Interface Interrupt Pin Output. Open-drain, active low output. A

low on INT indicates an unmasked management interrupt. This pin requires a

1.5 kΩ pull-up resistor to VDDIO.

MDIO

Management Data Input/Output Synchronous to the MDC Clock. This pin is

open-drain and requires a 1.5 kΩ pull-up resistor to VDDIO.

MDC

Management Data Clock Input up to 2.5 MHz.

Reset

RESET

Hardware Reset, Active Low Input. Hold low for >10 μs to reset the device.

This pin can be left floating if a hardware reset is not required. See the

Hardware Reset section.

Media Dependent Interface (MDI)

TXN

N/A

ADIN1101: Transmit/Receive Negative Pin

TXP

N/A

ADIN1101: Transmit/Receive Positive Pin.

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