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ADIN1101CCPZ-R7 Scheda tecnica(PDF) 70 Page - Analog Devices |
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ADIN1101CCPZ-R7 Scheda tecnica(HTML) 70 Page - Analog Devices |
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70 / 79 page  Data Sheet ADIN1101 REGISTER SUMMARY analog.com Rev. A | 70 of 79 Vendor Specific Device 1 and Vendor Specific Device 2 MMDs are present. Table 117. Bit Descriptions for MMD2_DEVS_IN_PKG2 Bits Bit Name Description Reset Access [15:0] MMD2_DEVS_IN_PKG2 Vendor Specific 2 MMD Devices in Package 2. Vendor Specific Device 1 and Vendor Specific Device 2 MMDs are present. 0xC000 R Vendor Specific MMD 2 Status Register Device Address: 0x1F; Register Address: 0x0008, Reset: 0x8000, Name: MMD2_STATUS This address corresponds to the Vendor Specific MMD 2 status register. Table 118. Bit Descriptions for MMD2_STATUS Bits Bit Name Description Reset Access [15:14] MMD2_STATUS Vendor Specific 2 MMD Status. 0x2 R 10 = device responding at this address. 11 = no device responding at this address. 01 = no device responding at this address. 00 = no device responding at this address. [13:0] RESERVED Reserved. 0x0 R PHY Subsystem Interrupt Status Register Device Address: 0x1F; Register Address: 0x0011, Reset: 0x0000, Name: PHY_SUBSYS_IRQ_STATUS This address can be read to check which interrupt events have occurred since the last time it was read. Each bit goes high when the associated event occurs and then latches high until it is unlatched by reading. The bits of PHY_SUBSYS_IRQ_STATUS go high even when the associated bits in PHY_SUBSYS_IRQ_MASK are not set. A reserved interrupt being triggered indicates a fatal error in the system. Table 119. Bit Descriptions for PHY_SUBSYS_IRQ_STATUS Bits Bit Name Description Reset Access 15 RESERVED Reserved. 0x0 R LH 14 MAC_IF_FC_FG_IRQ_LH MAC Interface Frame Checker/Generator Interrupt. 0x0 R LH 13 MAC_IF_EBUF_ERR_IRQ_LH MAC Interface Buffers Overflow/Underflow Interrupt. 0x0 R LH 12 RESERVED Reserved. 0x0 R LH 11 AN_STAT_CHNG_IRQ_LH Autonegotiation Status Change Interrupt. 0x0 R LH [10:2] RESERVED Reserved. 0x0 R LH 1 LINK_STAT_CHNG_LH Link Status Change. 0x0 R LH 0 RESERVED Reserved. 0x0 R LH PHY Subsystem Interrupt Mask Register Device Address: 0x1F; Register Address: 0x0021, Reset: 0x2402, Name: PHY_SUBSYS_IRQ_MASK Controls whether or not the interrupt signal is asserted in response to various events. Table 120. Bit Descriptions for PHY_SUBSYS_IRQ_MASK Bits Bit Name Description Reset Access 15 RESERVED Reserved. 0x0 R/W SC 14 MAC_IF_FC_FG_IRQ_EN Enable MAC Interface Frame Checker/Generator Interrupt. 0x0 R/W 13 MAC_IF_EBUF_ERR_IRQ_EN Enable MAC Interface Buffers Overflow/Underflow Interrupt. 0x1 R/W |
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