ISL85415

5. Detailed Description

FN8373 Rev.5.01

Page 19 of 30

Jun.4.20

5.

Detailed Description

The ISL85415 combines a synchronous buck PWM controller with integrated power switches. The buck controller

drives internal high-side and low-side N-channel MOSFETs to deliver load current up to 500mA. The buck

regulator can operate from an unregulated DC source, such as a battery, with a voltage ranging from +3V to +36V.

An internal LDO provides bias to the low voltage portions of the IC.

Peak current mode control is used to simplify feedback loop compensation and reject input voltage variation. User

selectable internal feedback loop compensation further simplifies design. The ISL85415 switches at a default

500kHz.

The buck regulator is equipped with an internal current sensing circuit and the peak current limit threshold is

typically set at 0.9A.

5.1

Power-On Reset

The ISL85415 automatically initializes upon receipt of the input power supply and continually monitors the EN pin

state. If EN is held below its logic rising threshold the IC is held in shutdown and consumes typically 1µA from the

VIN supply. If EN exceeds its logic rising threshold, the regulator enables the bias LDO and begin to monitor the

VCC pin voltage. When the VCC pin voltage clears its rising POR threshold the controller initializes the switching

regulator circuits. If VCC never clears the rising POR threshold, the controller does not allow the switching

regulator to operate. If VCC falls below its falling POR threshold while the switching regulator is operating, the

switching regulator shuts down until VCC returns.

5.2

Soft Start

To avoid large in-rush current, VOUT is slowly increased at start-up to its final regulated value. Soft-start time is

determined by the SS pin connection. If SS is pulled to VCC, an internal 2ms timer is selected for soft-start. For

other soft-start times, simply connect a capacitor from SS to GND. In this case, a 2µA current pulls up the SS

voltage and the FB pin follows this ramp until it reaches the 600mV reference level. Soft-start time for this case is

described by Equation 1:

5.3

Power-Good

PG is the open-drain output of a window comparator that continuously monitors the buck regulator output voltage

using the FB pin. PG is actively held low when EN is low and during the buck regulator soft-start period. After the

soft-start period completes, PG becomes high impedance provided the FB pin is within the range specified in the

“Electrical Specifications” on page 8. Should FB exit the specified window, PG is pulled low until FB returns.

Over-temperature faults also force PG low until the fault condition is cleared by an attempt to soft-start. There is

also an internal 5MΩ internal pull-up resistor.

5.4

PWM Control Scheme

The ISL85415 employs peak current-mode Pulse-Width Modulation (PWM) control for fast transient response and

pulse-by-pulse current limiting, as shown in the “Block Diagram” on page 4. The current loop consists of the

current sensing circuit, slope compensation ramp, PWM comparator, oscillator, and latch. Current sense

trans-resistance is typically 600mV/A and slope compensation rate, Se, is typically 450mV/T where T is the

switching cycle period. The control reference for the current loop comes from the error amplifier’s output (VCOMP).

A PWM cycle begins when a clock pulse sets the PWM latch and the upper FET is turned on. Current begins to

ramp up in the upper FET and inductor. This current is sensed (VCSA), converted to a voltage and summed with

the slope compensation signal. This combined signal is compared to VCOMP and when the signal is equal to

VCOMP, the latch is reset. Upon latch reset the upper FET is turned off and the lower FET turned on allowing

current to ramp down in the inductor. The lower FET remains on until the clock initiates another PWM cycle.

Figure 57 shows the typical operating waveforms during the PWM operation. The dotted lines illustrate the sum of

the current sense and slope compensation signal.

Time ms



CnF

0.3

=

(EQ. 1)