ISL85415

6. Protection Features

FN8373 Rev.5.01

Page 22 of 30

Jun.4.20

6.

Protection Features

The ISL85415 is protected from overcurrent, negative overcurrent, and over-temperature. The protection circuits

operate automatically.

6.1

Overcurrent Protection

During PWM on-time, current through the upper FET is monitored and compared to a nominal 0.9A peak

overcurrent limit. In the event that current reaches the limit, the upper FET turns off until the next switching cycle.

In this way, FET peak current is always well limited.

If the overcurrent condition persists for 17 sequential clock cycles, the regulator begins its hiccup sequence. In

this case, both FETS turn off and PG pulls low. This condition is maintained for eight soft-start periods; afterwards,

the regulator attempts a normal soft-start.

If the output fault persists, the regulator repeats the hiccup sequence indefinitely. There is no danger even if the

output is shorted during soft-start.

If VOUT is shorted very quickly, FB can collapse below 5/8ths of its target value before 17 cycles of overcurrent

are detected. The ISL85415 recognizes this condition and begins to lower its switching frequency proportional to

the FB pin voltage, which ensures the inductor current cannot run away (even with VOUT near 0V).

6.2

Negative Current Limit

If an external source somehow drives the current into VOUT, the controller attempts to regulate VOUT by reversing

its inductor current to absorb the externally sourced current. If the external source is low impedance, the current

can be reversed to unacceptable levels, and the controller initiates its negative current limit protection. Similar to

normal overcurrent, the negative current protection is realized by monitoring the current through the lower FET.

When the valley point of the inductor current reaches negative current limit, the lower FET is turned off and the

upper FET is forced on until current reaches the positive current limit or an internal clock signal is issued. At this

point, the lower FET is allowed to operate. If the current is pulled to the negative limit on the next cycle, the upper

FET is again forced on, and current is forced to 1/6th of the positive current limit. At this point, the controller turns

off both FET’s and waits for COMP to indicate return to normal operation. During this time, the controller applies a

100Ω load from PHASE to PGND and attempts to discharge the output. Negative current limit is a pulse-by-pulse

style operation, and recovery is automatic. Negative current limit protection is disabled in PFM operating mode

because reverse current is not allowed to build due to the diode emulation behavior of the lower FET.

6.3

Over-Temperature Protection

Over-temperature protection limits maximum junction temperature in the ISL85415. When the junction

temperature (TJ) exceeds +150°C, both FET’s are turned off and the controller waits for the temperature to

decrease by approximately 20°C. During this time, PG is pulled low. When temperature is within an acceptable

range, the controller initiates a normal soft-start sequence. For continuous operation, the +125°C junction

temperature rating should not be exceeded.

6.4

Boot Undervoltage Protection

If the boot capacitor voltage falls below 1.8V, the boot undervoltage protection circuit turns on the lower FET for

400ns to recharge the capacitor. This operation can arise during long periods of no switching such as PFM no

load situations. In PWM operation near dropout (VIN near VOUT), the regulator can hold the upper FET on for

multiple clock cycles. To prevent the boot capacitor from discharging, the lower FET is forced on for approximately

200ns every 10 clock cycles.