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ADMV1455BBCZ-R7 Scheda tecnica(PDF) 73 Page - Analog Devices

Il numero della parte ADMV1455BBCZ-R7
Spiegazioni elettronici  17.7GHz to 55GHz, Wideband, Microwave Downconverter
PDF  141 Pages
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Produttore elettronici  AD [Analog Devices]
Homepage  http://www.analog.com
Logo AD - Analog Devices

ADMV1455BBCZ-R7 Scheda tecnica(HTML) 73 Page - Analog Devices

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Data Sheet
ADMV1455
THEORY OF OPERATION
analog.com
Rev. 0 | 73 of 141
GAIN LUT
The digital logic contains a gain LUT with 67 indices that can be
used to determine the state of the DSAs and the GPO_G logic
outputs. This LUT can be beneficial for fast frequency hopping
applications, where it may be necessary to quickly change the chip
configuration states.
To use the LUT, set Register 0x285 to 1 and setup the LUT from
Register 0xE00 to Register 0xF0B.
There are three potential sources for the LUT index (pointer), as
determined by Register 0x286. The pointer can be set by using the
parallel logic input ADD_G balls, by using Register 0x282, or by
using the internal state machine. Set Register 0x286 to 0 to use
ADD_G balls as the pointer, set Register 0x286 to 1 to use Register
0x282 as the pointer, and set Register 0x286 to 2 to use the internal
state machine.
Regardless of LUT pointer source, use Register 0x298 to read back
the pointer value.
The LUT output values can be read from Register 0x28F to Regis-
ter 0x290. The values in these registers represent the DSA values
prior to the mux controlled by Register 0x285 and the LOAD
feature.
Gain State Machine
The internal state machine can be used to sequence through many
states, using the ADD_G5 input to advance and ADD_G4 to reset.
The state machine has several input parameters from the SPI, such
as offset value, stop value, step size, and reset.
At power up, the state machine output is zero, and it can be reset to
zero using either the ADD_G4 ball or Register 0x287. Set ADD_G4
to logic high to hold the state machine in reset and then bring to
logic low to re-enter normal operation. Alternatively, set Register
0x287 to 0 to hold the state machine in reset and then set it back to
1 to re-enter normal operation.
The step size is a 8-bit twos complement value, with a range
of −128 to +127, where −128 is represented by 0x80, +127 is
represented by 0x7F, and −1 is represented by 0xFF. A step size of
zero is invalid.
The state machine increments or decrements on each rising edge
of ADD_G5 based upon the step size value programmed. The
state machine is always bound by zero and the stop value. Once
it has reached one of these bounds, it remains there. When the
state machine value is equal to the stop value, changing the step
size from a positive number to a negative number allows the state
machine to be decremented back to zero.
The offset value is a 8-bit twos complement value, with a range
of −128 to +127, where −128 is represented by 0x80, +127 is
represented by 0x7F, and −1 is represented by 0xFF.
The pointer value is equal to the state machine value plus the offset
value. Use Register 0x288 to read back the current value of the
pointer.
Both the state machine value and the pointer value are bound by
zero and the stop value. If the state machine is left at a particular
value and the stop value or offset value is changed, then the pointer
may update provided it is within these bounds. The minimum
pointer value is bound by the offset value or zero, which ever is
greater.
Refer to Table 19 for the applicable registers and example state
machine behavior. The sequences shown in Table 19 continue do
not continue indefinitely for each rising edge on ADD_G5. The state
machine must be reset, the step size changed, or the stop value
changed to allow additional sequencing after it has reached the end
of a sequence.
Table 19. Gain State Machine Example Behavior
Example
Step1
Offset2
Stop3
State Machine Sequence
1
1
0
6
0, 1, 2, 3, 4, 5, 6
2
2
0
6
0, 2, 4, 6
3
4
0
6
0, 4, 6
4
6
0
6
0, 6
5
1
1
6
1, 2, 3, 4, 5, 6
6
2
1
6
1, 3, 5, 6
7
3
1
6
1, 4, 6
8
-1
0
6
6, 5, 4, 3, 2, 1, 0
1 The step size is determined by Register 0x283, Bits[7:0].
2 The offset is determined by Register 0x284, Bits[7:0].
3 The stop is determined by Register 0x289, Bits[6:0].



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