ADMV1455BBCZ-R7 datasheet(16/141 Pages) AD

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Data Sheet

ADMV1455

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

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Rev. 0 | 16 of 141

Table 17. Pin Function Descriptions (Continued)

Pin No.

Mnemonic

Description

DSA_IN

DSA1 RF Input. The DSA_IN ball is DC-coupled and matched to 50Ω. Do not apply an external voltage to

DSA_IN. If required, place a DC-blocking capacitor in series with DSA_IN and ensure that any capacitor

parasitic attributes are acceptable for the operating frequency range. If DSA1 is not used, the DSA_IN can

float.

B7, B8

BB_IN, BB_IP

Differential Baseband I Outputs. The outputs are internally DC-coupled with a 75Ω differential output

impedance, which allows the outputs to interface with either a 50Ω or 100Ω differential load impedance.

The common-mode voltage range is from 0.8V to 1.5V when VDD_BB = 2.5V and from 0.8V to 1.1V when

VDD_BB = 1.8V. When operating in the IF mode, BB_IN and BB_IP can float.

B10

GPO_G2

General-Purpose Digital Output Ball Gain 2. Active high, 1.8V logic. This ball can be left floating. Do not

ground this ball.

B11

GPO_G1

General-Purpose Digital Output Ball Gain 1. Active high, 1.8V logic. This ball can be left floating. Do not

ground this ball.

B12

GPO_G0

General-Purpose Digital Output Ball Gain 0. Active high, 1.8V logic. This ball can be left floating. Do not

ground this ball.

C10

BG_CAL

Band-Gap Reference Calibration. BG_CAL is used for factory and debug purposes. This ball can be left

floating or be tied to a 3.48kΩ, 1%, resistor. Do not ground this ball.

C11

GPO_F5

General-Purpose Digital Output Ball Filter 5. Active high, 1.8V logic. This ball can be left floating. Do not

ground this ball.

C12

GPO_F4

General-Purpose Digital Output Ball Filter 4. Active high, 1.8V logic. This ball can be left floating. Do not

ground this ball.

DSA_OUT

DSA1 RF output pin. This ball is DC-coupled and matched to 50Ω. Do not apply an external voltage to

DSA_OUT. If needed, place a DC-blocking capacitor in series with DSA_OUT, and be sure any capacitor

parasitic attributes are acceptable for the operating frequency range. If DSA1 is not used, the DSA_OUT

can float.

D6, E6

GPO_F3

General-Purpose Digital Output Ball Filter 3. Active high, 1.8V logic. This ball can be left floating. Do not

ground this ball.

D7, D8

ADD_F0

Frequency LUT Address Bit 0. Active high, 1.8V logic. No internal pull-up or pull-down resistance. Tie to

logic output from a microcontroller or field-programmable gate array (FPGA); do not float. If ADDF0 is not

used to set the look-up table address pointer, then please ground this ball.

CHIP_ADD1

Chip Address Bit 1. Active high, 1.8V logic. CHIP_ADD1 is internally pulled high through 15kΩ. This

ball can be dynamically set by logic output from a microcontroller or FPGA. For fixed addressing

implementations, set high by leave this ball floating, and set low by ground this ball. For single chip

implementations, always ground this ball.

D10

GPO_G3

General-Purpose Digital Output Ball Gain 3. Active high, 1.8V logic. This ball can be left floating. Do not

ground this ball.

D11

VDD_BB

Baseband Supply Voltage. For I/Q baseband mode, the nominal voltage is 2.5V, but this voltage can be

set to 1.8V if a lower gain is acceptable. The maximum P1dB performance is obtained by using 2.5V. For

the IF mode, the voltage can be 1.8V or 2.5 V, with no change in performance. Place 0.01μF and 1μF

decoupling capacitors close to VDD_BB.

E4, E5

GPO_F2

General-Purpose Digital Output Ball Filter 2. Active high, 1.8V logic. This ball can be left floating. Do not

ground this ball.

E8, E9

ADD_F1

Frequency LUT Address Bit 1. Active high, 1.8V logic. No internal pull-up or pull-down resistance. Tie to

logic output from a microcontroller or FPGA; do not float. If ADDF1 is not used to set the look-up table

address pointer, then please ground this ball.

RF_IN

RF input. This ball is DC-coupled and matched to 50Ω. Do not apply an external voltage to RF_IN.

If needed, place a DC-blocking capacitor in series with RF_IN, and be sure any capacitor parasitic

attributes are acceptable for the operating frequency range. When using DSA1, connect RF_IN directly to

DSA_OUT.

F7, F8

ADD_F4

Frequency LUT Address Bit 4. Active high, 1.8V logic. No internal pull-up or pull-down resistance. Tie to

logic output from a microcontroller or FPGA; do not float. If ADDF4 is not used to set the look-up table

address pointer, then please ground this ball.

F11

LO input. This ball is DC-coupled and matched to 50Ω. Do not apply an external voltage to LO. If

needed, place a DC-blocking capacitor in series with LO, and be sure any capacitor parasitic attributes are

acceptable for the operating frequency range.

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