ADMV1455BBCZ-R7 datasheet(79/141 Pages) AD

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Data Sheet

ADMV1455

THEORY OF OPERATION

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Rev. 0 | 79 of 141

I/Q BASEBAND GAIN SELECTION

The baseband amplifiers include two gain selection bits from Reg-

ister 0x194. Select the high gain setting for 50Ω differential load

impedance operating from DC to 8GHz, and select the low gain

setting for 100Ω differential load impedance operating from DC to

4GHz. For high gain selection, set the register to 3, and for low

gain selection, set the register to 0. The delta gain between the two

states is typically 6dB.

I/Q BASEBAND COMMON-MODE VOLTAGE

(VOCM)

The are two ways to set the I/Q baseband output VOCM, one is

through an internally generated voltage that is adjustable via the

SPI, and the other is through the CM_REF input. The acceptable

VOCM range is from 0.8V to 1.1V when the VDD_BB is 1.8V, and

this range can be extended to 1.5V when the VDD_BB voltage is

2.5V.

Set Register 0x18A, Bit 0, to 1 to use the internally generated

VOCM and set it to 0 when applying an external voltage to the

CM_REF ball. Ensure to include a shunt 0.01μF capacitor between

the CM_REF ball and ground when applying the external voltage.

When using the internally generated VOCM to adjust the voltage

on the BB_IP and BB_IN balls, use Register 0x15C, Bits[4:0]. For

adjusting the voltage of the BB_QP and BB_QN balls, use Register

0x165, Bits[4:0]. Figure 165 shows the typical VOCM vs. the VOCM

settings. Regardless of the VDD_BB supply setting, 1.8V or 2.5V,

the initial linear slope in the plot remains the same (for register

settings less than 14).

I/Q BASEBAND DC OFFSETS

Offset DC voltages can be introduced to each I/Q baseband output.

The offsets are controlled by eight registers, Register 0x18C to

approximately a 1.45mV step size, a 92mV range, and is across 64

states.

The eight registers are grouped into pairs, with the first register in

a pair setting the offset value and direction (positive or negative)

applied to the positive output ball, and then the second register in

a pair setting the opposite offset value and direction to the negative

output ball. Within a pair, the second register value must be set to

63 minus the value programmed into the first register.

The register pairs help maintain an average common-mode volt-

age between BB_IP and BB_IN, as well as between BB_QP and

BB_QN. For example, Register 0x18C introduces a positive offset

to the BB_IP ball, and Register 0x18D introduces a negative offset

to the BB_IN ball.

Only use a single register pair for BB_IP and BB_IN at a time.

Similarly, only use a single register pair for BB_QP and BB_QN

at a time. The unused register pairs must retain their default

corresponding output ball, as well as the offset direction.

Table 23. I/Q Baseband DC Offset Register Pairs

Pair

Bits Output Offset Direction

Value

0x18C

[5:0] BB_IP

Positive

User determined

0x18D

[5:0] BB_IN

Negative

63, Register 0x18C,

Bits[5:0]

0x18E

[5:0] BB_IP

Negative

User determined

0x18F

[5:0] BB_IN

Positive

63, Register 0x18E,

Bits[5:0]

0x190

[5:0] BB_QP Positive

User determined

0x191

[5:0] BB_QN Negative

63, Register 0x190,

Bits[5:0]

0x192

[5:0] BB_QP Negative

User determined

0x193

[5:0] BB_QN Positive

63, Register 0x192,

Bits[5:0]

IF SIGNAL CHAIN

The IF signal of the ADMV1455 supports frequencies from 2GHz

to 12GHz and consists of a 90° hybrid with fine adjust attenuators,

a tunable BPF with 4GHz of bandwidth, and two 15dB DSAs.

The IF_I and IF_Q quadrature outputs from the mixer feed into

two fine adjust attenuators that are then fed into the 90° hybrid.

The single-ended 90° hybrid output then drives the IF BPF, which

subsequently drives the DSAs. See Figure 177 for the IF signal

chain.

To use the IF signal chain, set Register 0x184 to 1. Power down the

baseband amplifiers by setting Register 0x107, Bits[3:0] to 1.

The IF signal chain output is internally DC-coupled with a 50Ω

single-ended impedance. When the IF signal chain is not used, the

IF ball can be left floating.

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