ADMV1455BBCZ-R7 datasheet(17/141 Pages) AD

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Data Sheet

ADMV1455

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

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Rev. 0 | 17 of 141

Table 17. Pin Function Descriptions (Continued)

Pin No.

Mnemonic

Description

G4, G5

GPO_F0

General-Purpose Digital Output Ball Filter 0. Active high, 1.8V logic. This ball can be left floating. Do not

ground this ball.

G6, H6

GPO_F1

General-Purpose Digital Output Ball Filter 1. Active high, 1.8V logic. This ball can be left floating. Do not

ground this ball.

G8, G9

ADD_F3

Frequency LUT Address Bit 3. Active high, 1.8V logic. No internal pull-up or pull-down resistance. Tie

ADD_F3 to the logic output from a microcontroller or FPGA; do not float. If ADD_F3 is not used to set the

LUT address pointer, ground this ball.

ADD_G2

Gain LUT Address Bit 2. Active high, 1.8V logic. No internal pull-up or pull-down resistance. Tie ADD_G2

to the logic output from a microcontroller or FPGA; do not float. If ADD_G2 is not used to set the LUT

address pointer, ground this ball.

ADD_G3

Gain LUT Address Bit 3. Active high, 1.8V logic. No internal pull-up or pull-down resistance. Tie ADD_G2

to the logic output from a microcontroller or FPGA; do not float. If ADD_G3 is not used to set the LUT

address pointer, ground this ball.

VDD_IF_1

IF Chain Supply Voltage, 1.8V. Place 0.01μF and 1μF decoupling capacitors close to VDD_IF.

H7, H8

ADD_F2

Frequency LUT Address Bit 2. Active high, 1.8V logic. No internal pull-up or pull-down resistance. Tie

ADD_F2 to the logic output from a microcontroller or FPGA; do not float. If ADD_F2 is not used to set the

LUT address pointer, ground this ball.

CHIP_ADD0

Chip Address Bit 0. Active high, 1.8V logic. CHIP_ADD0 is internally pulled high through 15kΩ. This

ball can be dynamically set by the logic output from a microcontroller or FPGA. For fixed addressing

implementations, set high by leaving this ball floating and set low by grounding this ball. For single chip

implementations, always ground this ball.

H10

LOAD

Load Synchronous Toggle. Active high, 1.8V logic. When the LOAD feature is enabled, transitioning the

LOAD ball from a logic low to logic high causes content in the filter and gain registers to be sent to the

working registers. Return the LOAD ball to logic low when the loading operation completes, see Figure

168 for more information. No internal pull-up or pull-down resistance. Tie LOAD to the logic output from a

microcontroller or FPGA; do not float. If LOAD feature is not used, ground this ball.

H11

SDIO

SPI Data Input and Output. Active high, 1.8V logic. For 3-wire SPI implementation, SDIO is bidirectional.

For 4-wire SPI implementation, SDIO is only used for data input.

ADD_G1

Gain LUT Address Bit 1. Active high, 1.8V logic. No internal pull-up or pull-down resistance. Tie ADD_G1

to the logic output from a microcontroller or FPGA; do not float. If ADD_G1 is not used to set the LUT

address pointer, ground this ball.

ADD_G4

Gain LUT Address Bit 4. Active high, 1.8V logic. No internal pull-up or pull-down resistance. Tie ADD_G4

to the logic output from a microcontroller or FPGA; do not float. If ADD_G4 is not used to set the LUT

address pointer, ground this ball.

J11

SDO

SPI Data Output. Active high, 1.8V logic. For 4-wire SPI implementations, SPI data is read using the SDO

ball. If SDO is not used, float this ball.

J12

SCLK

SPI Clock Input. Active high, 1.8V logic. During SPI write transactions, data is sampled on the rising edge

of SCLK. During SPI read transactions, output data changes at the falling edge of SCLK.

DVDD

Digital Supply Voltage, 1.8V. Place 0.01μF and 1μF decoupling capacitors close to DVDD.

ADD_G5

Gain LUT Address Bit 5. Active high, 1.8V logic. No internal pull-up or pull-down resistance. Tie ADD_G5

to the logic output from a microcontroller or FPGA; do not float. If ADD_G5 is not used to set the LUT

address pointer, ground this ball.

VDD_IF_2

IF Supply Voltage, 1.8V. Place 0.01μF and 1μF decoupling capacitors close to VDD_IF_2.

IF Output. The IF ball is DC-coupled and matched to 50Ω. Do not apply an external voltage to the IF ball. If

required, place a DC-blocking capacitor in series with IF and ensure that any capacitor parasitic attributes

are acceptable for the operating frequency range.

K7, K8

BB_QN, BB_QP

Differential Baseband Q Outputs. The outputs are internally DC-coupled with a 75Ω differential output

impedance, which allows the outputs to interface with either a 50Ω or 100Ω differential load impedance.

The common-mode voltage range is from 0.8V to 1.5V when VDD_BB = 2.5V and from 0.8V to 1.1V when

VDD_BB = 1.8V. When operating in IF mode, BB_QN and BB_QP can float.

K10

CEN

Chip Enable. Active high, 1.8V logic. No internal pull-up or pull-down resistance. Tie CEN to the logic

output from a microcontroller, FPGA, or power sequencer; do not float. The CEN pin must be held low until

all supply voltages have been turned on and RST has been set high.

K11

RST

Chip Reset. Active low, 1.8V logic.

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