ADMV1455BBCZ-R7 datasheet(10/141 Pages) AD

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Data Sheet

ADMV1455

SPECIFICATIONS

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Rev. 0 | 10 of 141

TIMING SPECIFICATIONS

See the Timing Diagrams Overview section, the Power-Up and Apply the Digital Inputs section, the Initialization SPI Instructions section,

the Chip Enable and Operation section, the Chip Disable and Reset section, and the Chip Disable and Power-Down section for additional

information.

Table 8. Timing Specifications

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

100

Power supplies 10% to 90% rise time.

Power supplies 90% level to valid digital input time (tDIGITAL). Do not set any logic input levels high prior

to tDIGITAL. The RST and CS can go high together after t2 has transpired. If CHIP_ADD0 and CHIP_ADD1

are to be set externally, then set them to the desired logic levels after t2 and prior to any SPI instructions.

RST rising edge to CS falling edge (first SPI instruction after reset). Waiting t3 ensures that the digital logic

has reset to the default values.

CS falling edge to SCLK rising edge setup time.

SCLK cycle time (write).

SCLK cycle time (read).

2.5

SCLK high time.

2.5

SCLK low time.

SDI data setup time.

SDI data hold time.

t10

SCLK rising edge to CS hold time.

t11

Minimum CS high time for latching in data (for multiple SPI transactions).

t12

CS rising edge to next SCLK rising edge ignore.

t13

SCLK falling edge to SDO valid (load capacitance (CL) = 10pF).

t14

SDO rise and fall time (CL = 10pF).

t15

CS rising edge to SDO tristate (CL = 10pF).

t16

Time from final initialization SPI instruction to entering the operational time (tOPERATIONAL). Set CEN to

logic high at this time.

t17

CS rising edge to LOAD pin first rising edge time for loading filter contents.

t18

LOAD pin high time for loading the filter and DSA contents.

t19

LOAD pin low time for preparing to load the DSA offsets.

t20

LOAD pin high time for loading the DSA offsets.

t21

CS falling edge to LOAD pin falling edge time. Both can be set low at the same time after a load operation

has been completed (after t18 or t20) and another SPI instruction is desired.

t22

Time from the last SPI instruction when the chip is operational (tCONTINUE)) to the disable time (tDISABLE).

After t22 has transpired, set CEN to logic low to disable the chip.

t23

μs

CEN falling edge to RST falling edge. Waiting t23 ensures that the RF portions of the chip have been

allowed to power down prior to chip reset.

t24

RST low time to perform reset.

t25

μs

CEN falling edge to the power-down time (tPOWER-DOWN). Waiting t25 ensures that the RF portions of the

chip have been allowed to power down prior to shutting down the chip power.

t26

μs

Logic inputs fall time. The logic inputs and power supplies can be turned off at the same time.

t27

100

Power supplies 90% to 10% fall time.

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