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FS26 Scheda tecnica(PDF) 53 Page - NXP Semiconductors

Il numero della parte FS26
Spiegazioni elettronici  Safety system basis chip with low power for ASIL D/ASIL B
PDF  156 Pages
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Produttore elettronici  NXP [NXP Semiconductors]
Homepage  http://www.nxp.com
Logo NXP - NXP Semiconductors

FS26 Scheda tecnica(HTML) 53 Page - NXP Semiconductors

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NXP Semiconductors
FS26
Safety system basis chip with low power for ASIL D/ASIL B
Bit
Symbol
Value
Description
Clear wake-up flags
0h
Do nothing
1h
Clear all wake-up flags
15
WU_CLR
Reset on power-on reset (POR_M), self-clear
Wake-up event source. Generates interrupt (INTB pulse)
0h
No wake up detected
1h
WAKE1
2h
WAKE2
3h
GPIO1
4h
GPIO2
5h
LDT expired
6h
SPI activity
8h
DFS Recovery
Fh
BATTERY fail: Reports when the device has lost valid VSUP and Main state machine is reset.
11 to 8
WUEVENT[3:0]
Reset on power-on reset (POR_M), go to standby mode, go to LPOFF mode, or WU_CLR write 1
LDT expired event flag
0h
Event not detected
1h
Event detected. Generates interrupt (INTB pulse)
4
LDT_I
Reset on power-on reset (POR_M), go to standby mode, go to LPOFF mode, or WU_CLR write 1
GPIO2 event flag
0h
No event on GPIO2
1h
Event on GPIO2 has occurred. Generates interrupt (INTB pulse)
3
GPIO2_I
Reset on power-on reset (POR_M), go to standby mode, go to LPOFF mode, or WU_CLR write 1
GPIO1 event flag
0h
No event on GPIO1
1h
Event on GPIO1 has occurred. Generates interrupt (INTB pulse)
2
GPIO1_I
Reset on power-on reset (POR_M), go to standby mode, go to LPOFF mode, or WU_CLR write 1
WAKE2 event flag
0h
No event on WAKE2
1h
Event on WAKE2 has occurred. Generates interrupt (INTB pulse)
1
WK2_I
Reset on power-on reset (POR_M), go to standby mode, go to LPOFF mode, or WU_CLR write 1
WAKE1 event flag
0h
No event on WAKE1
1h
Event on WAKE1 has occurred. Generates interrupt (INTB pulse)
0
WK1_I
Reset on power-on reset (POR_M), go to standby mode, go to LPOFF mode, or WU_CLR write 1
Table 35. M_WIO_FLG register bit description
16.2.11 M_WIO_MSK
Bit
15
14
13
12
11
10
9
8
Write
0
0
0
0
0
0
0
0
Read
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
Reset
0
0
0
0
0
0
0
0
Table 36. M_WIO_MSK register bit allocation
Bit
7
6
5
4
3
2
1
0
Write
0
0
0
LDT_M
GPIO2_M
GPIO1_M
WK2_M
WK1_M
FS26_SDS
All information provided in this document is subject to legal disclaimers.
© 2025 NXP B.V. All rights reserved.
Product short data sheet
Rev. 6.0 — 12 December 2025
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