FS26 datasheet(94/156 Pages) NXP

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NXP Semiconductors

FS26

Safety system basis chip with low power for ASIL D/ASIL B

18.3 VBST: boost controller

The VBST block is an asynchronous, current mode boost controller. VBST works in forced PWM mode. The

output voltage is configurable by OTP and the switching frequency is 450 kHz. A peak overcurrent detection

is implemented using the voltage sensed across RSNS_BST. The overcurrent detection can be selected with

VBST_ILIM_OTP[1:0] bitfield and the value is equal to VBST_ILIM_TH divided by RSNS_BST.

When the VBST_FB pin is disconnected, by means of VBST_FB < VBST_UV_TH, the boost controller is stopped

after tBST_UVOV. VBST will restart automatically when VBST_FB > VBST_UV_TH.

A maximum duty cycle protection is implemented in order to protect the boost controller in case of bad

component selection.

Two boost topologies (front-end and back-end) are supported:

In front-end mode (VBST_CFG_OTP = 0):

When VBST is used as the front-end supply, the battery voltage (VBAT) is applied at the input of the boost

controller. During normal operation with VSUP > VBST, the boost controller stops switching and operates in

Pass-Through mode. When VSUP drops below the VBST regulation threshold, the boost controller will start

switching to regulate the VSUP node to VBST.

NXP recommends setting the VBST output voltage between 6 V and 10 V maximum, to supply VPRE with

enough headroom during cranking pulses. If a higher output voltage is required for the application, the boost

should be used in back-end mode.

In the front-end configuration, VBST_OV_OTP must be set to 0 (Auto-enable). In Auto-enable mode, VBST

will stop switching automatically when VBST > VBST_OV_TH, and will resume switching when VBST drops

below VBST_OTP.

In the front-end configuration, the boost will be enabled only during cranking events. To avoid a latent fault,

the VBST_TMD bit can be used to force VBST to regulate at 17 V, no matter what the battery voltage is.

This allows verification of VBST availability using the VBST_S status flag.

An open drain output pin called VBST_PG is available to indicate the boost controller activity. This open

drain pin should be connected externally to the VDDIO voltage through a resistor. When VBST_PG is

high (open drain OFF) it indicates that the boost controller is switching. When VBST is operating in pulse

skipping mode, VBST_PG behavior may not be guaranteed. When VBST_PG is low (open drain ON) it

indicates that the boost controller is not switching or disabled.

The VBST current limitation is sensed at the input and therefore the current capability can be estimated

depending on VBST_IN, the VBST voltage configuration and the external components (LBST, RSNS_BST, DBST).

As an example, Table 102 summarizes the maximum current capability during a cranking operation using

LBST = 4.7 µH and the recommended RSNS_BST for COUT_BST = 40 µF.

FS26_SDS

All information provided in this document is subject to legal disclaimers.

Product short data sheet

Rev. 6.0 — 12 December 2025

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