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FS26 Scheda tecnica(PDF) 61 Page - NXP Semiconductors |
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FS26 Scheda tecnica(HTML) 61 Page - NXP Semiconductors |
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61 / 156 page ![]() NXP Semiconductors FS26 Safety system basis chip with low power for ASIL D/ASIL B 16.2.19 M_REG_CTRL2 Bit 15 14 13 12 11 10 9 8 Write 0 0 0 0 0 0 GPIO2LO GPIO1LO Reset 0 0 0 0 0 0 0 0 Table 52. M_REG_CTRL2 register bit allocation Bit 7 6 5 4 3 2 1 0 Write VREFDIS VBSTDIS 0 TRK2DIS TRK1DIS COREDIS LDO2DIS LDO1DIS Reset 0 0 0 0 0 0 0 0 Go to main register map Bit Symbol Value Description Request GPIO2 pin low 0h No effect (GPIO2 remains in current state) 1h GPIO2 set low 9 GPIO2LO Reset on power-on reset (POR_M), self-cleared Request GPIO1 pin low 0h No effect (GPIO1 remains in current state) 1h GPIO1 set low 8 GPIO1LO Reset on power-on reset (POR_M), self-cleared VREF disable request 0h No effect (regulator remain in its current state) 1h VREF disable request 7 VREFDIS Reset on power-on reset (POR_M), self-cleared VBST disable request 0h No effect (regulator remain in its current state) 1h VBST disable request 6 VBSTDIS Reset on power-on reset (POR_M), self-cleared TRK2 disable request 0h No effect (regulator remain in its current state) 1h TRK2 Disable request 4 TRK2DIS Reset on power-on reset (POR_M), self-cleared TRK1 disable request 0h No effect (regulator remain in its current state) 1h TRK1 disable request 3 TRK1DIS Reset on power-on reset (POR_M), self-cleared VCORE disable request 0h No effect (regulator remain in its current state) 1h VCORE disable request 2 COREDIS Reset on power-on reset (POR_M), self-cleared LDO2 disable request 0h No effect (regulator remain in its current state) 1h LDO2 disable request 1 LDO2DIS Reset on power-on reset (POR_M), self-cleared 0 LDO1DIS LDO1 disable request Table 53. M_REG_CTRL2 register bit description FS26_SDS All information provided in this document is subject to legal disclaimers. © 2025 NXP B.V. All rights reserved. Product short data sheet Rev. 6.0 — 12 December 2025 Document feedback 61 / 156 |
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