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FS26 Scheda tecnica(PDF) 64 Page - NXP Semiconductors |
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FS26 Scheda tecnica(HTML) 64 Page - NXP Semiconductors |
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64 / 156 page  NXP Semiconductors FS26 Safety system basis chip with low power for ASIL D/ASIL B Bit Symbol Description Long Duration Timer (LDT) after-run configuration register LDT after-run target value in normal mode 15 to 0 LDT_AFTER_RUN[15:0] Reset on power-on reset (POR_M), LDT count started Table 57. M_LDT_CFG1 register bit description 16.2.22 M_LDT_CFG2 Bit 15 14 13 12 11 10 9 8 Write LDT_WUP_L[15:8] Read LDT_WUP_L[15:8] Reset 0 0 0 0 0 0 0 0 Table 58. M_LDT_CFG2 register bit allocation Bit 7 6 5 4 3 2 1 0 Write LDT_WUP_L[7:0] Read LDT_WUP_L[7:0] Reset 0 0 0 0 0 0 0 0 Go to main register map Bit Symbol Description 16 less significant bits of Wake-up with Long Duration Timer 16 less significant bits for the wake up with the Long Duration Timer 15 to 0 LDT_WUP_L[15:0] Reset on power-on reset (POR_M), LDT Count started Table 59. M_LDT_CFG2 register bit description 16.2.23 M_LDT_CFG3 Bit 15 14 13 12 11 10 9 8 Write 0 0 0 0 0 0 0 0 Read 0 0 0 0 0 0 0 0 Reset 0 0 0 0 0 0 0 0 Table 60. M_LDT_CFG3 register bit allocation Bit 7 6 5 4 3 2 1 0 Write LDT_WUP_H[7:0] Read LDT_WUP_H[7:0] Reset 0 0 0 0 0 0 0 0 Go to main register map Bit Symbol Description 8 more significant bits of Long Duration Timer Wake-up Timer 8 most significant bit for the wake up with the Long Duration Timer 7 to 0 LDT_WUP_H[7:0] Reset on power-on reset (POR_M), LDT Count started Table 61. M_LDT_CFG3 register bit description FS26_SDS All information provided in this document is subject to legal disclaimers. © 2025 NXP B.V. All rights reserved. Product short data sheet Rev. 6.0 — 12 December 2025 Document feedback 64 / 156 |
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