FS26 datasheet(78/156 Pages) NXP

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NXP Semiconductors

FS26

Safety system basis chip with low power for ASIL D/ASIL B

Bit

Bit Group Name

Description

Value

Settings

19h

4.45 V

1Ah

4.50 V

1Bh

4.55 V

1Ch

4.60 V

1Dh

4.65 V

1Eh

4.70 V

1Fh

4.75 V

20h

4.80 V

21h

4.85 V

22h

4.90 V

23h

4.95 V

24h

5.00 V

25h

5.05 V

26h

5.10 V

27h

5.15 V

28h

5.20 V

29h

5.25 V

2Ah

5.30 V

2Bh

5.35 V

Table 82. OTP_VPRE_VOLT3 register bit description...continued

Go to main OTP configuration map

17.2.15 OTP_CORE_CFG1

Bit

Bit Group Name

Description

Value

Settings

Rise = 5 V/ns; Fall = 2.2 V/ns

Rise = 4 V/ns; Fall = 0.6 V/ns

Rise = 4.5 V/ns; Fall = 1.2 V/ns

5 to 4

COREHS_SR_OTP[1:0]

VCORE high-side slew rate

tCORESW_HSSRR / tCORESW_HSSRF

Rise = 5 V/ns; Fall = 2.2 V/ns

No delay

1 clock cycle

2 clock cycles

3 to 2

CORE_PH_OTP[1:0]

VCORE phase delay

3 clock cycles

1.4 A

1.7 A

2.7 A

1 to 0

CORE_ILIM_OTP[1:0]

VCORE current limit

ICORE_PEAK_0A8

ICORE_PEAK_1A65

3.4 A

Table 83. OTP_CORE_CFG1 register bit description

Go to main OTP configuration map

17.2.16 OTP_CORE_CFG2

Bit

Bit Group Name

Description

Value

Settings

150 kΩ

5 to 4

CORE_RCOMP_OTP[1:0]

VCORE comp resistance

200 kΩ

Table 84. OTP_CORE_CFG2 register bit description

FS26_SDS

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Product short data sheet

Rev. 6.0 — 12 December 2025

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