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FS26 Scheda tecnica(PDF) 15 Page - NXP Semiconductors |
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FS26 Scheda tecnica(HTML) 15 Page - NXP Semiconductors |
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15 / 156 page ![]() NXP Semiconductors FS26 Safety system basis chip with low power for ASIL D/ASIL B 8 Pinning information 8.1 Pinning EXPOSED PAD VBST_PG VMONPRE WAKE 2 VBOS GPIO1 CORE_IN TRK1 CORE_BT TRK2 CORE_SW GPIO2 DEBUG TRKIN CORE_FB VREF AMUX LDO2OUT CSB LDOIN SCLK LDO1OUT MOSI Power management Communication Safety Other FS1B MISO 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 aaa-045500 Figure 7. Pin assignment in LQFP48 package with exposed pad 8.2 Pin descriptions Symbol Pin Number Type Description VBST_PG 1 Digital output Power Good signal of VBST WAKE2 2 Analog input WAKE2 input pin or ERRMON input GPIO1 3 Analog output / Digital Input General Purpose I/O 1 (GPIO1) TRK1 4 Analog output TRK1 regulator output TRK2 5 Analog output TRK2 regulator output GPIO2 6 Analog output / Digital Input General Purpose I/O 2 (GPIO2) TRKIN 7 Analog input TRK1, TRK2 and VREF regulators input VREF 8 Analog output Voltage reference output (VREF) LDO2OUT 9 Analog output LDO2 output LDOIN 10 Analog input LDO1 and LDO2 regulator input voltage supply LDO1OUT 11 Analog output LDO1 regulator output FS1B 12 Digital output Safety output #1 (FS01) Table 3. Pin descriptions FS26_SDS All information provided in this document is subject to legal disclaimers. © 2025 NXP B.V. All rights reserved. Product short data sheet Rev. 6.0 — 12 December 2025 Document feedback 15 / 156 |
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