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FS26 Scheda tecnica(PDF) 139 Page - NXP Semiconductors

Il numero della parte FS26
Spiegazioni elettronici  Safety system basis chip with low power for ASIL D/ASIL B
PDF  156 Pages
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Produttore elettronici  NXP [NXP Semiconductors]
Homepage  http://www.nxp.com
Logo NXP - NXP Semiconductors

FS26 Scheda tecnica(HTML) 139 Page - NXP Semiconductors

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NXP Semiconductors
FS26
Safety system basis chip with low power for ASIL D/ASIL B
VMON_PRE_OVDGLT_OTP
VMON_PRE overvoltage deglitch
45 μs
45 μs
45 μs
45 μs
45 μs
45 μs
VMON_PRE_UVDGLT_OTP[1:0]
VMON_PRE undervoltage deglitch
40 μs
40 μs
40 μs
25 μs
40 μs
40 μs
VCORE_V_OTP[7:0]
VMON_CORE monitoring voltage
1.50 V
1.50 V
1.50 V
1.50 V
1.25 V
1.50 V
VMON_CORE_OVTH_OTP[3:0]
VMON_CORE overvoltage threshold
104.5 %
108.00 %
106 %
106 %
106 %
106 %
VMON_CORE_UVTH_OTP[3:0]
VMON_CORE undervoltage threshold
95.5 %
95.5 %
94.00 %
94.00 %
94.00%
94.00 %
VMON_CORE_OVDGLT_OTP
VMON_CORE overvoltage deglitch
45 μs
45 μs
45 μs
45 μs
45 μs
45 μs
VMON_CORE
configuration
VMON_CORE_UVDGLT_OTP[1:0]
VMON_CORE undervoltage deglitch
40 μs
40 μs
40 μs
25 μs
40 μs
40 μs
LDO1_V_OTP
VMON_LDO1 monitoring voltage
5.0 V
3.3 V
5.0 V
5.0 V
5.0 V
5.0 V
VMON_LDO1_OVTH_OTP[3:0]
VMON_LDO1 overvoltage threshold
106.00 %
108.00 %
107.50 %
107.50 %
106.00 %
107.50 %
VMON_LDO1_UVTH_OTP[3:0]
VMON_LDO1 undervoltage threshold
94.00 %
91.00 %
92.50 %
93.00 %
94.00 %
92.50 %
VMON_LDO1_UVDTH_OTP
VMON_LDO1 Degraded UV Monitoring
Normal UV
Normal UV
Normal UV
Normal UV
Normal UV
Normal UV
VMON_LDO1_OVDGLT_OTP
VMON_LDO1 overvoltage deglitch
45 μs
45 μs
45 μs
45 μs
45 μs
45 μs
VMON_LDO1_UVDGLT_OTP[1:0]
VMON_LDO1 undervoltage deglitch
40 μs
40 μs
40 μs
25 μs
40 μs
40 μs
VMON_LDO1
configuration
LDO1_PLIFT_DIS_OTP
LDO1 pin lift detection
LDO1 pin lift
detection enabled
LDO1 pin lift
detection enabled
LDO1 pin lift
detection enabled
LDO1 pin lift
detection enabled
LDO1 pin lift
detection enabled
LDO1 pin lift
detection enabled
LDO2_V_OTP
VMON_LDO2 monitoring voltage
3.3 V
5.0 V
3.3 V
3.3 V
3.3 V
3.3 V
VMON_LDO2_OVTH_OTP[3:0]
VMON_LDO2 overvoltage threshold
106.00 %
104.5 %
106.00 %
106.00 %
106.00 %
106.00 %
VMON_LDO2_UVTH_OTP[3:0]
VMON_LDO2 undervoltage threshold
94.00 %
95.5 %
94.00 %
94.00 %
94.00 %
94.00 %
VMON_LDO2_UVDTH_OTP
VMON_LDO2 Degraded UV Monitoring
Normal UV
Normal UV
Normal UV
Normal UV
Normal UV
Normal UV
VMON_LDO2_OVDGLT_OTP
VMON_LDO2 overvoltage deglitch
45 μs
45 μs
45 μs
45 μs
45 μs
45 μs
VMON_LDO2_UVDGLT_OTP[1:0]
VMON_LDO2 undervoltage deglitch
40 μs
40 μs
40 μs
25 μs
40 μs
40 μs
VMON_LDO2
configuration
LDO2_PLIFT_DIS_OTP
LDO2 pin lift detection
LDO2 pin lift
detection enabled
LDO2 pin lift
detection enabled
LDO2 pin lift
detection enabled
LDO2 pin lift
detection enabled
LDO2 pin lift
detection enabled
LDO2 pin lift
detection enabled
TRK1_V_OTP[1:0]
VMON_TRK1 monitoring voltage
5.0 V
5.0 V
5.0 V
5.0 V
3.3 V
3.3 V
VMON_TRK1_OVTH_OTP[3:0]
VMON_TRK1 overvoltage threshold
104.5 %
108.00 %
106 %
107.50 %
106.00 %
106 %
VMON_TRK1_UVTH_OTP[3:0]
VMON_TRK1 undervoltage threshold
95.5 %
92.00 %
94 %
93.00 %
94 %
94 %
VMON_TRK1_OVDGLT_OTP
VMON_TRK1 overvoltage deglitch
45 μs
45 μs
45 μs
45 μs
45 μs
45 μs
VMON_TRK1
configuration
VMON_TRK1_UVDGLT_OTP[1:0]
VMON_TRK1 undervoltage deglitch
40 μs
40 μs
40 μs
25 μs
40 μs
40 μs
TRK2_V_OTP[1:0]
VMON_TRK2 monitoring voltage
3.3 V
5.0 V
5.0 V
3.3 V
3.3 V
3.3 V
VMON_TRK2_OVTH_OTP[3:0]
VMON_TRK2 overvoltage threshold
104.5 %
108.00 %
106 %
106 %
104.50 %
106 %
VMON_TRK2_UVTH_OTP[3:0]
VMON_TRK2 undervoltage threshold
95.5 %
92.00 %
94.00 %
94.00 %
95.50 %
94.00 %
VMON_TRK2_OVDGLT_OTP
VMON_TRK2 overvoltage deglitch
45 μs
45 μs
45 μs
45 μs
45 μs
45 μs
VMON_TRK2
configuration
VMON_TRK2_UVDGLT_OTP[1:0]
VMON_TRK2 undervoltage deglitch
40 μs
40 μs
40 μs
25 μs
40 μs
40 μs
VREF_V_OTP
VMON_VREF monitoring voltage
5.0 V
3.3 V
5.0 V
5.0 V
3.3 V
3.3 V
VMON_VREF_OVTH_OTP[3:0]
VMON_VREF overvoltage threshold
104.50 %
105.00 %
104.50 %
105.00 %
105.00 %
104.50 %
VMON_VREF_UVTH_OTP[3:0]
VMON_VREF undervoltage threshold
95.50 %
95.00 %
95.50 %
95.00 %
95.00 %
95.50 %
VMON_VREF_OVDGLT_OTP
VMON_REF overvoltage deglitch
45 μs
45 μs
45 μs
45 μs
45 μs
45 μs
VMON_REF
configuration
VMON_VREF_UVDGLT_OTP[1:0]
VMON_REF undervoltage deglitch
40 μs
40 μs
40 μs
25 μs
40 μs
40 μs
Table 127. OTP configurations...continued
FS26_SDS
All information provided in this document is subject to legal disclaimers.
© 2025 NXP B.V. All rights reserved.
Product short data sheet
Rev. 6.0 — 12 December 2025
Document feedback
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