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LMKDB1108FS Scheda tecnica(PDF) 25 Page - Texas Instruments

Il numero della parte LMKDB1108FS
Spiegazioni elettronici  LMKDB11xx PCIe Gen 1 to Gen 7 Ultra Low Jitter LP-HCSL Clock Buffer Family
PDF  133 Pages
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Produttore elettronici  TI2 [Texas Instruments]
Homepage  https://www.ti.com
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LMKDB1108FS Scheda tecnica(HTML) 25 Page - Texas Instruments

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6.5 Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VOH,DC
Output voltage high with DC test load
DB2000QL DC test load(2)
225
270
mV
VOL,DC
Output voltage low with DC test load
10
150
mV
Vovs,DC
Output overshoot voltage with DC test
load
75
mV
Vuds,DC
Output undershoot voltage with DC test
load
–75
mV
Zdiff
Differential output impedance
Measured at VOL/VOH, VDD = 3.3 V
80.75
85
89.25
Ω
Measured at VOL/VOH, VDD = 1.8 V
81
85
90
Ω
Zdiff
Differential output impedance
Measured at VOL/VOH, VDD = 3.3 V, TA=
0
℃ to 105℃
80.75
85
89.25
Ω
Measured at VOL/VOH, VDD = 1.8 V, TA=
0
℃ to 105℃
81
85
90
Ω
Zdiff
Differential output impedance
Min swing, VDD = 3.3 V
80
88.5
Ω
Zdiff
Differential output impedance
Max swing, VDD = 3.3 V
86.5
106.5
Ω
Zdiff
Differential output impedance
Min swing, VDD = 1.8 V
80
89
Ω
Zdiff
Differential output impedance
Max swing, VDD = 1.8 V
88
112.5
Ω
Zdiff-
crossing
Differential output impedance - crossing
Measured during transition
68
85
102
Ω
dV/dt
Output slew rate
Min swing. Default slew rate setting
2.4
2.85
V/ns
dV/dt
Output slew rate
Max swing. Default slew rate setting
3.5
4.8
V/ns
dV/dt
Output slew rate
Measured from –150 mV to +150 mV
on the differential waveform. Lowest slew
rate(6) (7)
1.3
2.2
V/ns
Measured from –150 mV to +150 mV on
the differential waveform. Low slew rate(6)
(7)
2.5
3
V/ns
Measured from –150 mV to +150 mV on
the differential waveform. High slew rate
(default)(6) (7)
3
3.5
V/ns
Measured from –150 mV to +150 mV on
the differential waveform. Highest slew
rate(6) (7)
2.4
4
V/ns
∆dV/dt
Rising edge rate to falling edge rate
matching
DB2000QL AC test load(6)
10
%
DCD
Duty cycle distortion
Measured on the differential waveform.
Input duty cycle = 50%(6)
–1
1
%
Vcross,AC Absolute crossing point voltage
DB2000QL AC test load(6)
250
550
mV
Vcross,DC Absolute crossing point voltage
DB2000QL DC test load(2)
130
200
mV
∆Vcross,A
C
Variation of Vcross over all clock edges
DB2000QL AC test load(6)
140
mV
∆Vcross-
DC
Variation of Vcross over all clock edges
DB2000QL DC test load(2)
35
mV
|VRB|
Absolute value of ring back voltage as
defined in PCIe
DB2000QL AC test load(6)
100
mV
VRB
Ring back voltage as defined in DB800ZL DB2000QL AC test load(6)
–200
200
mV
tstable
Time before VRB is allowed
DB2000QL AC test load(6)
500
ps
CLOCK OUTPUT CHARACTERISTICS - non-PCIe (LMKDB1120FS, LMKDB1108FS, LMKDB1104FS)
VOH
Output voltage high
Output swing programmed to 800 mV. f0
= 156.25 MHz or 312.5 MHz
720
890
mV
VOL
Output voltage low
–120
120
mV
www.ti.com
LMKDB1102, LMKDB1104, LMKDB1104FS, LMKDB1108, LMKDB1108FS
LMKDB1112, LMKDB1120, LMKDB1120FS
SNAS855G – NOVEMBER 2023 – REVISED MAY 2026
Copyright © 2026 Texas Instruments Incorporated
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Product Folder Links: LMKDB1102 LMKDB1104 LMKDB1104FS LMKDB1108 LMKDB1108FS LMKDB1112 LMKDB1120 LMKDB1120FS



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