LMKDB1108FS datasheet(59/133 Pages) TI2

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9.2 LMKDB1112 Registers

Table 9-29 lists the memory-mapped registers for the LMKDB1112 registers. All register offset addresses not

listed in Table 9-29 should be considered as reserved locations and the register contents should not be modified.

Table 9-29. LMKDB1112 Registers

Offset

Acronym

Section

Output Enable Control for CLK0 through CLK5

Section 9.2.1

Output Enable Control for CLK6 through CLK11

Section 9.2.2

OE Pin Readback for CLK0 through CLK5

Section 9.2.3

OE Pin Readback for CLK6 through CLK11

Section 9.2.4

ACP Enable Control and SBI_EN Readback

Section 9.2.5

Device Info

Section 9.2.6

Device Info (cont.)

Section 9.2.7

SMBus Byte Counter

Section 9.2.8

SBI Mask for CLK0 through CLK5

Section 9.2.9

SBI Mask for CLK6 through CLK11

Section 9.2.10

R11

SBI Readback for CLK0 through CLK5

Section 9.2.11

R12

SBI Readback for CLK6 through CLK11

Section 9.2.12

11h

R17

Output Amplitude Control

Section 9.2.13

12h

R18

Input Receiver Bias and Termination Resistor Control

Section 9.2.14

14h

R20

Output Slew Rate Select MSB for CLK0 through CLK5

Section 9.2.15

15h

R21

Output Slew Rate Select MSB for CLK6 through CLK11

Section 9.2.16

26h

R38

Non-clearable SMBus Write Lock

Section 9.2.17

27h

R39

LOS Status and Clearable SMBus Write Lock

Section 9.2.18

5Bh

R91

Slew Rate Speed Options 1 and 2 Assignments

Section 9.2.19

5Ch

R92

Slew Rate Speed Options 3 and 4 Assignments

Section 9.2.20

61h

R97

Slew Rate Mode Selection

Section 9.2.21

62h

R98

Output Slew Rate Select LSB for CLK0 through CLK5

Section 9.2.22

63h

R99

Output Slew Rate Select LSB for CLK6 through CLK11

Section 9.2.23

Complex bit access types are encoded to fit into small table cells. Table 9-30 shows the codes that are used for

access types in this section.

Table 9-30. LMKDB1112 Access Type Codes

Access Type

Code

Description

Read Type

Read

Write Type

Write

WMC

Write

WSC

Write

Reset or Default Value

-n

Value after reset or the default

value

9.2.1 R0 Register (Offset = 0h) [Reset = B7h]

R0 is shown in Table 9-31.

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LMKDB1102, LMKDB1104, LMKDB1104FS, LMKDB1108, LMKDB1108FS

LMKDB1112, LMKDB1120, LMKDB1120FS

SNAS855G – NOVEMBER 2023 – REVISED MAY 2026

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