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LMKDB1108FS Scheda tecnica(PDF) 79 Page - Texas Instruments

Il numero della parte LMKDB1108FS
Spiegazioni elettronici  LMKDB11xx PCIe Gen 1 to Gen 7 Ultra Low Jitter LP-HCSL Clock Buffer Family
PDF  133 Pages
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LMKDB1108FS Scheda tecnica(HTML) 79 Page - Texas Instruments

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9.3.22 R98 Register (Offset = 62h) [Reset = D0h]
R98 is shown in Table 9-77.
Return to the Summary Table.
Table 9-77. R98 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
SLEWRATE_SEL_CLK7_
LSB
R/W
1h
LSB CLK7 slew rate select
6
SLEWRATE_SEL_CLK8_
LSB
R/W
1h
LSB CLK8 slew rate select
5:4
RESERVED
R
0h
Reserved
3
SLEWRATE_SEL_CLK9_
LSB
R/W
0h
LSB CLK9 slew rate select
2
SLEWRATE_SEL_CLK10
_LSB
R/W
0h
LSB CLK10 slew rate select
1
SLEWRATE_SEL_CLK11
_LSB
R/W
0h
LSB CLK11 slew rate select
0
SLEWRATE_SEL_CLK12
_LSB
R/W
0h
LSB CLK12 slew rate select
0
SLEWRATE_SEL_CLK6_
LSB
R/W
0h
LSB CLK6 slew rate select
9.3.23 R99 Register (Offset = 63h) [Reset = F6h]
R99 is shown in Table 9-78.
Return to the Summary Table.
Table 9-78. R99 Register Field Descriptions
Bit
Field
Type
Reset
Description
6
SLEWRATE_SEL_CLK0_
LSB
R/W
1h
LSB CLK0 slew rate select
5
SLEWRATE_SEL_CLK1_
LSB
R/W
1h
LSB CLK1 slew rate select
4
SLEWRATE_SEL_CLK2_
LSB
R/W
1h
LSB CLK2 slew rate select
3
SLEWRATE_SEL_CLK3_
LSB
R/W
1h
LSB CLK3 slew rate select
2
SLEWRATE_SEL_CLK4_
LSB
R/W
1h
LSB CLK4 slew rate select
1
SLEWRATE_SEL_CLK5_
LSB
R/W
1h
LSB CLK5 slew rate select
0
RESERVED
R
0h
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LMKDB1102, LMKDB1104, LMKDB1104FS, LMKDB1108, LMKDB1108FS
LMKDB1112, LMKDB1120, LMKDB1120FS
SNAS855G – NOVEMBER 2023 – REVISED MAY 2026
Copyright © 2026 Texas Instruments Incorporated
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Product Folder Links: LMKDB1102 LMKDB1104 LMKDB1104FS LMKDB1108 LMKDB1108FS LMKDB1112 LMKDB1120 LMKDB1120FS



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