LMKDB1108FS datasheet(99/133 Pages) TI2

99 / 133 page

10 Application and Implementation

Note

Information in the following applications sections is not part of the TI component specification,

and TI does not warrant its accuracy or completeness. TI’s customers are responsible for

determining suitability of components for their purposes, as well as validating and testing their design

implementation to confirm system functionality.

10.1 Application Information

The LMKDB devices are a family of ultra-low additive jitter LP-HCSL clock buffers and clock MUX. The device

can be controlled through SMBus registers, Side Band Interface, and OE# pins.

10.2 Typical Application

This example shows PCIe and Ethernet clock distribution. Provide multiple copies of PCIe clocks (100MHz) or

Ethernet clocks (156.25MHz) based on the given source.

PCIe Clock Source #1

LMKDB family

PCIe Clock Buffer or MUX

SMBus

Control

OE#

Control

PCIe PHY

LP-HCSL

PCIe PHY

PCIe Device

Side-Band

Interface

Control Interface

PCIe Clock Source #2

MUX only, optional

Figure 10-1. Typical Application

10.2.1 Design Requirements

Find two buffers for PCIe clock fan-out and Ethernet clock fan-out separately. Jitter requirements must be met

and space must be minimized.

Table 10-1. Design Parameters

PARAMETER

VALUE

Number of PCIe clocks

Number of 156.25MHz Ethernet clocks

PCIe architecture

CC (Common Clock)

PCIe reference clock slew rate

≥3.5V/ns

PCIe Gen 5 reference clock jitter

45fs maximum

PCIe Gen 5 total jitter

50fs maximum

156.25MHz reference clock slew rate

≥3.5V/ns

156.25MHz reference clock jitter (12kHz to 20MHz)

90fs maximum

156.25MHz total jitter (12kHz to 20MHz)

100fs maximum

10.2.2 Detailed Design Procedure

First of all, calculate the jitter budget for the clock buffer using RMS addition. The maximum allowed additive

jitter for the clock buffer is square root of the difference between square of reference clock jitter and square of

total clock jitter.

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SNAS855G – NOVEMBER 2023 – REVISED MAY 2026

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