LMKDB1108FS datasheet(33/133 Pages) TI2

33 / 133 page

6.5 Electrical Characteristics (continued)

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

VIL

SMB_CLK, SMB_DATA input low voltage

0.3 ×

VDD

VHYS

Hysteresis of Schmitt Trigger Inputs

0.05 ×

VDD

VOL

SMB_DATA output low voltage

IOL = 4 mA

0.4

ILEAK

SMB_CLK, SMB_DATA input leakage

–10

µA

CPIN

SMB_CLK, SMB_DATA pin capacitance

(1)

PCIe AC test load

(2)

DB2000QL DC test load

(3)

First clock edge is used for timing measurements. Clock outputs are muted until stabilized.

(4)

For input pins, assertion or deassertion starts when the input voltage reaches the minimum voltage required for a "high" level, or the

maximum voltage required for a "low" level

(5)

All power supply pins are tied together. A 0.1µF capacitor is placed close to each power supply pin. 50 mVpp ripple is applied before

the decoupling capacitors. Measure the spur level at the clock output

(6)

DB2000QL AC test load

(7)

Slew rate is highly dependent on PCB trace characteristics

6.6 SMBus Timing Requirements

100kHz CLASS

400kHz CLASS

UNIT

MIN

MAX

MIN

MAX

fSMB

SMBus Operating Frequency

100

400

kHz

fBUF

Bus free time between STOP and START

condition

4.7

–

1.3

–

μs

tHD_STA

Hold time after (REPEATED) START condition

4.0

–

0.6

–

μs

tSU_STA

REPEATED START condition setup time

4.7

–

0.6

–

μs

tSU_STO

STOP condition setup time

4.0

–

0.6

–

μs

tHD_DAT

Data hold time

–

tSU_DAT

Data setup time

250

–

100

–

tTIMEOUT

Detect clock low timeout

tLOW

Clock low period

4.7

–

1.3

–

μs

tHIGH

Clock high period

4.0

0.6

μs

tLOW_SEXT

Cumulative clock low extend time (secondary

device)

–

tLOW_PEXT

Cumulative clock low extend time (primary

device)

–

Clock/Data Fall Time

–

300

–

300

Clock/Data Rise Time

–

1000

–

300

tSPIKE

Noise spike suppression time

–

tPOR

Time in which a device must be operational after

power-on reset

500

6.7 SBI Timing Requirements

MIN

MAX

UNIT

tPERIOD

Clock period

tSETUP

SHFT setup to SBI_CLK rising edge

–

tDSU

SBI_IN data setup to SBI_CLK rising edge

–

tDHOLD

SBI_IN data hold after SBI_CLK rising edge

–

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SNAS855G – NOVEMBER 2023 – REVISED MAY 2026

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