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LMKDB1108FS Scheda tecnica(PDF) 64 Page - Texas Instruments

Il numero della parte LMKDB1108FS
Spiegazioni elettronici  LMKDB11xx PCIe Gen 1 to Gen 7 Ultra Low Jitter LP-HCSL Clock Buffer Family
PDF  133 Pages
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Produttore elettronici  TI2 [Texas Instruments]
Homepage  https://www.ti.com
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LMKDB1108FS Scheda tecnica(HTML) 64 Page - Texas Instruments

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Table 9-43. R17 Register Field Descriptions
Bit
Field
Type
Reset
Description
7:4
AMP
R/W
6h
Global Differential output Control = 0.6V to approximately 1V
25mV/step Default = 0.75V
0h = 600mV
1h = 625mV
2h = 650mV
3h = 675mV
4h = 700mV
5h = 725mV
6h = 750mV
7h = 775mV
8h = 800mV
9h = 825mV
Ah = 850mV
Bh = 875mV
Ch = 900mV
Dh = 925mV
Eh = 950mV
Fh = 975mV
3:0
RESERVED
R
0h
Reserved bits
9.2.14 R18 Register (Offset = 12h) [Reset = 08h]
R18 is shown in Table 9-44.
Return to the Summary Table.
Table 9-44. R18 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
d_RX_EN_AC_INPUT
R/W
0h
Enable receiver bias when CLKIN is AC coupled
0h = DC coupled input
1h = AC coupled input
6
d_RX_EN_RTERM_LSB
R/W
0h
Enable termination resistors on CLKIN
0h = Input Termination R is disabled
1h = Input Termination R is enabled
5:4
RESERVED
R
0h
Reserved bits
3
PD_RESTOREB
R/W
1h
Save Configuration in Power Down
0h = Config Cleared
1h = Config Saved
2:1
RESERVED
R
0h
Reserved bits
0
LOSb_RB
R
0h
Real time read back of loss detect block output
0h = LOS event detected
1h = NO LOS event detected
9.2.15 R20 Register (Offset = 14h) [Reset = B7h]
R20 is shown in Table 9-45.
Return to the Summary Table.
Table 9-45. R20 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
SLEWRATE_SEL_CLK5_
_MSB
R/W
1h
MSB CLK5 slew rate select
6
RESERVED
R
0h
Reserved bits
5
SLEWRATE_SEL_CLK4_
_MSB
R/W
1h
MSB CLK4 slew rate select
LMKDB1102, LMKDB1104, LMKDB1104FS, LMKDB1108, LMKDB1108FS
LMKDB1112, LMKDB1120, LMKDB1120FS
SNAS855G – NOVEMBER 2023 – REVISED MAY 2026
www.ti.com
64
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Product Folder Links: LMKDB1102 LMKDB1104 LMKDB1104FS LMKDB1108 LMKDB1108FS LMKDB1112 LMKDB1120 LMKDB1120FS



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