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R5F572TFGDFP Scheda tecnica(PDF) 53 Page - Renesas Technology Corp

Il numero della parte R5F572TFGDFP
Spiegazioni elettronici  Renesas MCUs
PDF  120 Pages
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Produttore elettronici  RENESAS [Renesas Technology Corp]
Homepage  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

R5F572TFGDFP Scheda tecnica(HTML) 53 Page - Renesas Technology Corp

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R01DS0331EJ0110 Rev.1.10
Page 53 of 120
Oct 06, 2023
RX72T Group
2. Electrical Characteristics
Note 1. Supply current values are measured when all output pins are unloaded and all input pull-up resistors are disabled.
Note 2. Peripheral module clocks are supplied. This does not include operations as BGO (background operations).
Note 3. ICC depends on f (ICLK) as follows.
(when ICLK : PCLKA : PCLKB : PCLKC : PCLKD : BCLK : BCLK pin = 8 : 4 : 2 : 8 : 2 : 2 : 1 and EXTAL = 20 MHz)
• G version product
ICC Max. = 0.535 × f + 29 (full operation in normal operating mode)
ICC Typ. = 0.115 × f + 5 (normal operation in normal operating mode)
ICC Max. = 0.155 × f + 29 (sleep mode)
Note 4. This does not include operations as BGO (background operations). Whether the peripheral module clocks are supplied or
stopped is controlled only by the bit settings in the module stop control registers A to D.
Note 5. When peripheral module clocks are stopped, each clock frequency is set for division by 64, and the frequencies of FCLK, BCLK,
PCLKA, PCLKB, PCLKC, PCLKD, and the BCLK pin are the same.
Note 6. This is an increase caused by program/erase operation to the code flash memory or data flash memory during executing the
user program.
Table 2.7
DC Characteristics (3) (G version)
Conditions: VCC = 2.7 to 5.5 V, VCC_USB = 2.7 to 5.5 V, AVCC0 = AVCC1 = AVCC2 = 3.0 to 5.5V,
VSS = VSS_USB = AVSS0 = AVSS1 = AVSS2 = 0 V,
Ta = Topr
Item
Symbol
G version
Unit
Test Conditions
Min.
Typ.
Max.
Supply
current*1
Full operation*2
ICC*3
—
—
136
mA
ICLK = 200 MHz
PCLKA = 100 MHz
PCLKB = 50 MHz
PCLKC = 200 MHz
PCLKD = 50 MHz
FCLK = 50 MHz
BCLK = 50 MHz
BCLK pin = 25 MHz
Normal
operation
Peripheral module clocks are supplied*4
—28—
Peripheral module clocks are stopped
*4, *5
—16—
CoreMark
Peripheral module clocks are stopped
*4, *5
—27—
Sleep mode: Peripheral module clocks are
supplied*4
—23
60
All module clock stop mode (reference value)
—
10.9
46
Increase current by BGO operation*6
—14—
Increase current by operating Trusted Secure IP
—
3.9
5.3
Software standby mode
—
0.9
22.1
VOLSR.PGAVLS = 1
Deep software standby mode
—
15
28
µA
VOLSR.PGAVLS = 1



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