R5F572TFGDFP datasheet(98/120 Pages) RENESAS

98 / 120 page

R01DS0331EJ0110 Rev.1.10

Page 98 of 120

Oct 06, 2023

RX72T Group

2. Electrical Characteristics

2.4.6.11

RIIC

Note:

tIICcyc: RIIC internal reference clock (IICφ) cycle

Note 1. The value within parentheses is applicable when the value of the ICMR3.NF[1:0] bits is 11b while the digital filter is enabled by

the setting ICFER.NFE = 1.

Note 2. Cb is the total capacitance of the bus lines.

Note 3. When VCC ≥ 4.5V, VOLSR.RICVLS = 0

When VCC < 4.5V, VOLSR.RICVLS = 1

Table 2.40

RIIC Timing

Conditions: VCC = 2.7 to 5.5 V, VCC_USB = 2.7 to 5.5 V, AVCC0 = AVCC1 = AVCC2 = 3.0 to 5.5V,

VSS = VSS_USB = AVSS0 = AVSS1 = AVSS2 = 0 V, Ta = Topr,

ICLK = 8 to 200 MHz, PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, PCLKC = 8 to 200 MHz, BCLK = 8 to 60 MHz,

High-drive output is selected by the driving ability control register (other than for P53 to P55 and P60 to P65).

Item

Symbol

Min.*1

Max.*1

Unit

Test

Conditions*3

RIIC

(Standard-mode,

SMBus)

SCL input cycle time

tSCL

6(12) × tIICcyc + 1300

—

Figure 2.60

SCL input high pulse width

tSCLH

3(6) × tIICcyc + 300

—

SCL input low pulse width

tSCLL

3(6) × tIICcyc + 300

—

SCL, SDA input rise time

tSr

—1000

SCL, SDA input fall time

tSf

—300

SCL, SDA input spike pulse removal time

tSP

1(4) × tIICcyc

SDA input bus free time

tBUF

3(6) × tIICcyc + 300

—

Start condition input hold time

tSTAH

tIICcyc + 300

—

Restart condition input setup time

tSTAS

1000

—

Stop condition input setup time

tSTOS

1000

—

Data input setup time

tSDAS

tIICcyc + 50

—

Data input hold time

tSDAH

0—

SCL, SDA capacitive load

—

400

RIIC

(Fast-mode)

SCL input cycle time

tSCL

6(12) × tIICcyc + 600

—

SCL input high pulse width

tSCLH

3(6) × tIICcyc + 300

—

SCL input low pulse width

tSCLL

3(6) × tIICcyc + 300

—

SCL, SDA input rise time

tSr

20 × (External pull-up

voltage/5.5V)

300

SCL, SDA input fall time

tSf

20 × (External pull-up

voltage/5.5V)

300

SCL, SDA input spike pulse removal time

tSP

1(4) × tIICcyc

SDA input bus free time

tBUF

3(6) × tIICcyc + 300

—

Start condition input hold time

tSTAH

tIICcyc + 300

—

Restart condition input setup time

tSTAS

300

—

Stop condition input setup time

tSTOS

300

—

Data input setup time

tSDAS

tIICcyc + 50

—

Data input hold time

tSDAH

0—

SCL, SDA capacitive load

—

400

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