R5F572TFGDFP datasheet(89/120 Pages) RENESAS

89 / 120 page

R01DS0331EJ0110 Rev.1.10

Page 89 of 120

Oct 06, 2023

RX72T Group

2. Electrical Characteristics

Note 1. tPAcyc: PCLKA cycle, tPBcyc: PCLKB cycle

Table 2.38

Simple SPI Timing

Conditions: VCC = 2.7 to 5.5 V, VCC_USB = 2.7 to 5.5 V, AVCC0 = AVCC1 = AVCC2 = 3.0 to 5.5V,

VSS = VSS_USB = AVSS0 = AVSS1 = AVSS2 = 0 V, Ta = Topr,

ICLK = 8 to 200 MHz, PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, PCLKC = 8 to 200 MHz, BCLK = 8 to 60 MHz,

Output load conditions: VOH = 0.5 × VCC, VOL = 0.5 × VCC, C = 30 pF,

High-drive output is selected by the driving ability control register (other than for P53 to P55 and P60 to P65).

Item

Symbol

Min.

Max.

Unit*1

Test

Conditions

Simple

SPI

(SCI11)

SCK clock cycle output (master)

tSPcyc

65536

tPAcyc

Figure 2.48

SCK clock cycle input (slave)

—

SCK clock high pulse width

tSPCKWH

0.4

0.6

tSPcyc

SCK clock low pulse width

tSPCKWL

0.4

0.6

tSPcyc

SCK clock rise/fall time

tSPCKr, tSPCKf

—20

Data input setup time

tSU

33.3

—

Figure 2.49 to

Figure 2.52

Data input hold time

33.3

—

SS input setup time

tLEAD

1—

tSPcyc

SS input hold time

tLAG

1—

tSPcyc

Data output delay time

tOD

—

33.3

Data output hold time

tOH

–10

—

Data rise/fall time

tDr, tDf

—

16.6

SS input rise/fall time

tSSLr, tSSLf

—

16.6

Slave access time

tSA

—7

tPAcyc

Figure 2.51,

Figure 2.52

Slave output release time

tREL

—7

tPAcyc

Simple

SPI

(SCI1,

SCI5,

SCI6,

SCI8,

SCI9,

SCI12)

SCK clock cycle output (master)

tSPcyc

65536

tPBcyc

Figure 2.48

SCK clock cycle input (slave)

—

SCK clock high pulse width

tSPCKWH

0.4

0.6

tSPcyc

SCK clock low pulse width

tSPCKWL

0.4

0.6

tSPcyc

SCK clock rise/fall time

tSPCKr, tSPCKf

—20

Data input setup time

tSU

33.3

—

Figure 2.49 to

Figure 2.52

Data input hold time

33.3

—

SS input setup time

tLEAD

1—

tSPcyc

SS input hold time

tLAG

1—

tSPcyc

Data output delay time

tOD

—

33.3

Data output hold time

tOH

–10

—

Data rise/fall time

tDr, tDf

—

16.6

SS input rise/fall time

tSSLr, tSSLf

—

16.6

Slave access time

tSA

—7

tPBcyc

Figure 2.51,

Figure 2.52

Slave output release time

tREL

—7

tPBcyc

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