R5F572TFGDFP datasheet(79/120 Pages) RENESAS

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R01DS0331EJ0110 Rev.1.10

Page 79 of 120

Oct 06, 2023

RX72T Group

2. Electrical Characteristics

2.4.6.4

POE

Note 1. tPBcyc: PCLKB cycle

Figure 2.27

POE Input Timing

Figure 2.28

Output Disable Time for POE in Response to Transition of the POEn# Signal Level

Table 2.31

POE Timing

Conditions: VCC = 2.7 to 5.5 V, VCC_USB = 2.7 to 5.5 V, AVCC0 = AVCC1 = AVCC2 = 3.0 to 5.5V,

VSS = VSS_USB = AVSS0 = AVSS1 = AVSS2 = 0 V, Ta = Topr,

ICLK = 8 to 200 MHz, PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, PCLKC = 8 to 200 MHz, BCLK = 8 to 60 MHz,

Output load conditions: VOH = 0.5 × VCC, VOL = 0.5 × VCC, C = 30 pF,

High-drive output is selected by the driving ability control register (other than for P53 to P55 and P60 to P65).

Item

Symbol

Min.

Typ.

Max.

Unit*1

Test Conditions

POE

POEn# input pulse width

(n = 0, 4, and 8 to 14)

tPOEW

1.5

—

tPBcyc Figure 2.27

Output disable time

Transition of the POEn#

signal level

tPOEDI

—

5 PCLKB + 0.24

µs

Figure 2.28

When detecting falling edges

(ICSRm.POEnM[3:0] = 0000b

(m = 1 to 5, 7 to 9, n = 0, 4, 8 to

14))

Simultaneous conduction

of output pins

tPOEDO

—

3 PCLKB + 0.2

µs

Figure 2.29

Detection of comparator

outputs

tPOEDC

—

5 PCLKB + 0.2

µs

Figure 2.30

The time is that when the noise

filter for comparator C is not in

use (CMPCTL.CDFS[1:0] = 00b)

and excludes the time for

detection by comparator C.

tPOEDS

—

1 PCLKB + 0.2

µs

Figure 2.31

Time for access to the register is

not included.

Oscillation stop detection

tPOEDOS

—

µs

Figure 2.32

POEn# input

(n = 0, 4, 8 to 14)

PCLKB

tPOEW

POEn# input

(n = 0, 4, 8 to 14)

MTU PWM output pins

GPTW PWM output pins

Outputs disabled

tPOEW

tPOEDI

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