R5F572TFGDFP datasheet(81/120 Pages) RENESAS

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R01DS0331EJ0110 Rev.1.10

Page 81 of 120

Oct 06, 2023

RX72T Group

2. Electrical Characteristics

2.4.6.5

POEG

Note 1. tPBcyc: PCLKB cycle

Figure 2.33

POEG Input Timing

Table 2.32

POE and POEG Timing

Conditions: VCC = 2.7 to 5.5 V, VCC_USB = 2.7 to 5.5 V, AVCC0 = AVCC1 = AVCC2 = 3.0 to 5.5V,

VSS = VSS_USB = AVSS0 = AVSS1 = AVSS2 = 0 V, Ta = Topr,

ICLK = 8 to 200 MHz, PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, PCLKC = 8 to 200 MHz, BCLK = 8 to 60 MHz,

Output load conditions: VOH = 0.5 × VCC, VOL = 0.5 × VCC, C = 30 pF,

High-drive output is selected by the driving ability control register (other than for P53 to P55 and P60 to P65).

Item

Symbol

Min.

Typ.

Max.

Unit*1

Test Conditions

POEG

GTETRGn input pulse width (n = A to D)

tPOEGW

1.5

—

tPBcyc Figure 2.33

Output disable time

Input level detection of the

GTETRGn pin (via flag)

tPOEGDI

—

3 PCLKB + 0.34

µs

Figure 2.34

When the digital noise filter is not

in use (POEGGn.NFEN = 0

(n = A to D))

Detection of the output

stopping signal from

GPTW (deadtime error,

simultaneous high output,

or simultaneous low out-

put)

tPOEGDE

—

0.5

µs

Figure 2.35

Edge detection signal from

a comparator

tPOEGDC

—

4 PCLKB + 0.5

µs

Figure 2.36

The time is that when the noise

filter for comparator C is not in

use (CMPCTL.CDFS[1:0] = 00b)

and excludes the time for

detection by comparator C.

tPOEGDS

—

1 PCLKB + 0.3

µs

Figure 2.37

Time for access to the register is

not included.

Oscillation stop detection

tPOEGDOS

—

µs

Figure 2.38

Input level detection of the

GTETRGn pin (direct path)

tPOEGDDI

—

2 PCLKB +

1 PCLKC + 0.34

µs

Figure 2.39

Level detection signal from

a comparator

tPOEGDDC

—

3 PCLKB + 0.3

µs

Figure 2.40

The time is that when the noise

filter for comparator C is not in

use (CMPCTL.CDFS[1:0] = 00b)

and excludes the time for

detection by comparator C.

GTETRGn input

(n = A to D)

PCLKB

tPOEGW

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