R5F572TFGDFP datasheet(76/120 Pages) RENESAS

76 / 120 page

R01DS0331EJ0110 Rev.1.10

Page 76 of 120

Oct 06, 2023

RX72T Group

2. Electrical Characteristics

2.4.6

Timing of On-Chip Peripheral Modules

2.4.6.1

I/O Port

Note 1. tPBcyc: PCLKB cycle

Figure 2.23

I/O Port Input Timing

2.4.6.2

TMR

Note 1. tPBcyc: PCLKB cycle

Table 2.28

I/O Port Timing

Conditions: VCC = 2.7 to 5.5 V, VCC_USB = 2.7 to 5.5 V, AVCC0 = AVCC1 = AVCC2 = 3.0 to 5.5V,

VSS = VSS_USB = AVSS0 = AVSS1 = AVSS2 = 0 V, Ta = Topr,

ICLK = 8 to 200 MHz, PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, PCLKC = 8 to 200 MHz, BCLK = 8 to 60 MHz,

Output load conditions: VOH = 0.5 × VCC, VOL = 0.5 × VCC, C = 30 pF,

High-drive output is selected by the driving ability control register (other than for P53 to P55 and P60 to P65).

Item

Symbol

Min.

Max.

Unit*1

Test

Conditions

I/O ports

Input data pulse width

tPRW

1.5

—

tPBcyc

Figure 2.23

Table 2.29

TMR Timing

Conditions: VCC = 2.7 to 5.5 V, VCC_USB = 2.7 to 5.5 V, AVCC0 = AVCC1 = AVCC2 = 3.0 to 5.5V,

VSS = VSS_USB = AVSS0 = AVSS1 = AVSS2 = 0 V, Ta = Topr,

ICLK = 8 to 200 MHz, PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, PCLKC = 8 to 200 MHz, BCLK = 8 to 60 MHz,

Output load conditions: VOH = 0.5 × VCC, VOL = 0.5 × VCC, C = 30 pF,

High-drive output is selected by the driving ability control register (other than for P53 to P55 and P60 to P65).

Item

Symbol

Min.

Max.

Unit*1

Test

Conditions

TMR

Timer clock pulse width

Single-edge

setting

tTMCWH,

tTMCWL

1.5

—

tPBcyc

Figure 2.24

Both-edge

setting

2.5

—

Port

PCLKB

tPRW

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