R5F572TFGDFP datasheet(80/120 Pages) RENESAS

Il numero della parte	R5F572TFGDFP

Spiegazioni elettronici	Renesas MCUs

PDF	120 Pages

Scroll/Zoom	100%

Produttore elettronici	RENESAS [Renesas Technology Corp]

Homepage	http://www.renesas.com

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80 / 120 page

R01DS0331EJ0110 Rev.1.10

Page 80 of 120

Oct 06, 2023

RX72T Group

2. Electrical Characteristics

Figure 2.29

Output Disable Time for POE in Response to the Simultaneous Conduction of Output

Pins

Figure 2.30

Output Disable Time for POE in Response to Detection of the Comparator Outputs

Figure 2.31

Output Disable Time for POE in Response to the Register Setting

Figure 2.32

Output Disable Time for POE in Response to the Oscillation Stop Detection

Outputs

disabled

Simultaneous active-level outputs detected*1

Note 1. When the active level is set to low.

MTU PWM output pins

GPTW PWM output pins

tPOEDO

COMPn level detection

signal (n = 0 to 5)

MTU PWM output pins

GPTW PWM output pins

Outputs disabled

tPOEDC

MTU PWM output pins

GPTW PWM output pins

Outputs disabled

tPOEDS

Corresponding bit in

the SPOER register

Oscillation stop detection

signal (internal signal)

MTU PWM output pins

GPTW PWM output pins

Outputs disabled

tPOEDOS

Main clock

R5F572TFGDFP Scheda tecnica(PDF) 80 Page - Renesas Technology Corp