HD404369F datasheet(40/117 Pages) RENESAS

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HD404369 Series

Oscillator Circuit

A block diagram of the clock generation circuit is shown in figure 22. As shown in table 20, a ceramic

oscillator or crystal oscillator can be connected to OSC

1 and OSC2, and a 32.768-kHz oscillator can be

connected to X1 and X2. The system oscillator can also be operated by an external clock.

Registers for Oscillator Circuit Operation

System Clock Selection Register 1 (SSR1: $027): Four bit write-only register which sets the subsystem

clock frequency (f

SUB) division ratio, and sets the subsystem clock oscillation in stop mode. Bit 1 (SSR11)

of system clock select register 1 must be set according to the frequency of the oscillator connected to OSC

and OSC

2 (figure 23).

Bit 1 (SSR11) and bit 2 (SSR12) are initialized to 0 on reset and in stop mode. Bit 3 (SSR13) is initialized

to 0 only on reset.

OSC2

OSC1

System

oscillator

Sub-

system

oscillator

1/4, 1/8,

1/16 or

1/32

division

circuit*1

Timing

generator

circuit

System

clock

selection

CPU with ROM,

RAM, registers,

flags, and I/O

Peripheral

function

interrupt

Time-base

interrupt

Time-base

clock

selection

1/8 or 1/4

division

circuit*2

Timing

generator

circuit

Timing

generator

circuit

1/8

division

circuit

fSUB

tsubcyc

LSON

TMA3

fcyc

tcyc

fOSC

tWcyc

øCPU

øPER

øCLK

Notes:

1/4, 1/8, 1/16 or 1/32 division ratio can be selected by setting bits 0 and 1 of system clock

select register 2 (SSR2: $028).

1/8 or 1/4 division ratio can be selected by setting bit 2 of system clock select register 1

(SSR1: $027).

Figure 22 Clock Generation Circuit

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