HD404369F datasheet(77/117 Pages) RENESAS

77 / 117 page

HD404369 Series

The output level of the SO pin is invalid until the first data is output after MCU reset, or until the output

level control in idle states is performed.

Transfer Control: The serial interface is activated by the STS instruction. The octal counter is reset to 000

by this instruction, and it increments at the rising edge of the transmit clock. When the eighth transmit

clock signal is input or when serial transmission/receive is discontinued, the octal counter is reset to 000,

the serial interrupt request flag (IFS: $003, bit 2) is set, and the transfer stops.

When the prescaler output is selected as the transmit clock, the transmit clock frequency is selected as 4t

cyc

to 8192t

cyc by setting bits 0 to 2 (SMR0– SMR2) of serial mode register (SMR: $005) and bit 0 (PMRC0)

of port mode register C (PMRC: $025) as listed in table 28.

Operating States: The serial interface has the following operating states; transitions between them are

shown in figure 59.

 STS wait state

 Transmit clock wait state

 Transfer state

 Continuous clock output state (only in internal clock mode)

• STS wait state: The serial interface enters STS wait state by MCU reset (00, 10 in figure 59). In STS

wait state, the serial interface is initialized and the transmit clock is ignored. If the STS instruction is

then executed (01, 11), the serial interface enters transmit clock wait state.

• Transmit clock wait state: Transmit clock wait state is the period between the STS execution and the

falling edge of the first transmit clock. In transmit clock wait state, input of the transmit clock (02, 12)

increments the octal counter, shifts the serial data register, and puts the serial interface in transfer state.

However, note that if continuous clock output mode is selected in internal clock mode, the serial

interface does not enter transfer state but enters continuous clock output state (17).

The serial interface enters STS wait state by writing data to the serial mode register (SMR: $005) (04,

14) in transmit clock wait state.

• Transfer state: Transfer state is the period between the falling edge of the first clock and the rising edge

of the eighth clock. In transfer state, the input of eight clocks or the execution of the STS instruction

sets the octal counter to 000, and the serial interface enters another state. When the STS instruction is

executed (05, 15), transmit clock wait state is entered. When eight clocks are input, transmit clock wait

state is entered (03) in external clock mode, and STS wait state is entered (13) in internal clock mode. In

internal clock mode, the transmit clock stops after outputting eight clocks.

In transfer state, writing data to the serial mode register (SMR: $005) (06, 16) initializes the serial

interface, and STS wait state is entered.

If the state changes from transfer to another state, the serial interrupt request flag (IFS: $003, bit 2) is set

by the octal counter that is reset to 000.

• Continuous clock output state (only in internal clock mode): Continuous clock output state is entered

only in internal clock mode. In this state, the serial interface does not transmit/receive data but only

outputs the transmit clock from the

SCK pin.

HD404369F Scheda tecnica(PDF) 77 Page - Renesas Technology Corp

HD404369F Scheda tecnica(HTML) 77 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Scheda tecnica Scarica

Link URL