HD404369F datasheet(78/117 Pages) RENESAS

78 / 117 page

HD404369 Series

When bits 0 and 1 (PMRA0, PMRA1) of port mode register A (PMRA: $004) are 00 in transmit clock

wait state and if the transmit clock is input (17), the serial interface enters continuous clock output state.

If the serial mode register (SMR: $005) is written to in continuous clock output mode (18), STS wait

state is entered.

Output Level Control in Idle States: In idle states, that is, STS wait state and transmit clock wait state,

the output level of the SO pin can be controlled by setting bit 1 (PMRC1) of port mode register C (PMRC:

$025) to 0 or 1. The output level control example is shown in figure 60. Note that the output level cannot be

controlled in transfer state.

Transmit Clock Error Detection (In External Clock Mode): The serial interface will malfunction if a

spurious pulse caused by external noise conflicts with a normal transmit clock during transfer. A transmit

clock error of this type can be detected as shown in figure 61.

Table 27

Serial Interface Operating Modes

SMR

PMRA

Bit 3

Bit 1

Bit 0

Operating Mode

Continuous clock output mode

Transmit mode

Receive mode

Transmit/receive mode

Table 28

Serial Transmit Clock (Prescaler Output)

PMRC

SMR

Bit 0

Bit 2

Bit 1

Bit 0

Prescaler Division Ratio

Transmit Clock Frequency

÷ 2048

4096t

cyc

÷ 512

1024t

cyc

÷ 128

256t

cyc

÷ 32

64t

cyc

÷ 8

16t

cyc

÷ 24t

cyc

÷ 4096

8192t

cyc

÷ 1024

2048t

cyc

÷ 256

512t

cyc

÷ 64

128t

cyc

÷ 16

32t

cyc

÷ 48t

cyc

HD404369F Scheda tecnica(PDF) 78 Page - Renesas Technology Corp

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