HD404369F datasheet(59/117 Pages) RENESAS

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HD404369 Series

Timer B

Timer B Functions: Timer B has the following functions.

• Free-running/reload timer

• External event counter

• Input capture timer

The block diagram for each operation mode of timer B is shown in figures 38 and 39.

Timer B Operations:

• Free-running/reload timer operation: The free-running/reload operation, input clock source, and

prescaler division ratio are selected by timer mode register B1 (TMB1: $009).

Timer B is initialized to the value set in timer write register B (TWBL: $00A, TWBU: $00B) by

software and incremented by one at each clock input. If an input clock is applied to timer B after it has

reached $FF, an overflow is generated. In this case, if the reload timer function is enabled, timer B is

initialized to its initial value set in timer write register B; if the free-running timer function is enabled,

the timer is initialized to $00 and then incremented again.

The overflow sets the timer B interrupt request flag (IFTB: $002, bit 0). IFTB is reset by software or

MCU reset. Refer to figure 3 and table 1 for details.

• External event counter operation: Timer B is used as an external event counter by selecting the external

event input as an input clock source. In this case, pin D

2/EVNB must be set to EVNB by port mode

Either falling or rising edge, or both falling and rising edges of input signals can be selected as the

external event detection edge by timer mode register 2 (TMB2: $026). When both rising and falling

edges detection is selected, the time between the falling edge and rising edge of input signals must be

cyc or longer.

Timer B is incremented by one at each detection edge selected by timer mode register 2 (TMB2: $026).

The other operation is basically the same as the free-running/reload timer operation.

• Input capture timer operation: The input capture timer counts the clock cycles between trigger edges

input to pin EVNB.

Either falling or rising edge, or both falling and rising edges of input signals can be selected as the

trigger input edge by timer mode register 2 (TMB2: $026).

When a trigger edge is input to EVNB, the count of timer B is written to timer read register B (TRBL:

$00A, TRBU: $00B), and the timer B interrupt request flag (IFTB: $002, bit 0) and the input capture

status flag (ICSF: $021, bit 0) are set. Timer B is reset to $00, and then incremented again. While ICSF

is set, if a trigger input edge is applied to timer B, or if timer B generates an overflow, the input capture

error flag (ICEF: $021, bit 1) is set. ICSF and ICEF are reset to 0 by MCU reset or by writing 0.

HD404369F Scheda tecnica(PDF) 59 Page - Renesas Technology Corp