HD404369F datasheet(17/117 Pages) RENESAS

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HD404369 Series

SPX Register (SPX), SPY Register (SPY): Four-bit registers used to supplement the X and Y registers.

Carry Flag (CA): One-bit flag that stores any ALU overflow generated by an arithmetic operation. CA is

affected by the SEC, REC, ROTL, and ROTR instructions. A carry is pushed onto the stack during an

interrupt and popped from the stack by the RTNI instruction—but not by the RTN instruction.

Status Flag (ST): One-bit flag that latches any overflow generated by an arithmetic or compare instruction,

not-zero decision from the ALU, or result of a bit test. ST is used as a branch condition of the BR, BRL,

CAL, and CALL instructions. The contents of ST remain unchanged until the next arithmetic, compare, or

bit test instruction is executed, but become 1 after the BR, BRL, CAL, or CALL instruction is read,

regardless of whether the instruction is executed or skipped. The contents of ST are pushed onto the stack

during an interrupt and popped from the stack by the RTNI instruction—but not by the RTN instruction.

Program Counter (PC): 14-bit binary counter that points to the ROM address of the instruction being

executed.

Stack Pointer (SP): Ten-bit pointer that contains the address of the stack area to be used next. The SP is

initialized to $3FF by MCU reset. It is decremented by 4 when data is pushed onto the stack, and

incremented by 4 when data is popped from the stack. The top four bits of the SP are fixed at 1111, so a

stack can be used up to 16 levels.

The SP can be initialized to $3FF in another way: by resetting the RSP bit with the REM or REMD

instruction.

Reset

The MCU is reset by inputting a low-level voltage to the

RESET pin. At power-on or when stop mode is

cancelled,

RESET must be low for at least one t

RC to enable the oscillator to stabilize. During operation,

RESET must be low for at least two instruction cycles.

Initial values after MCU reset are listed in table 1.

Interrupts

The MCU has 7 interrupt sources: two external signals (

INT

0 and INT1), three timer/counters (timers A, B,

and C), serial interface, and A/D converter.

An interrupt request flag (IF), interrupt mask (IM), and vector address are provided for each interrupt

source, and an interrupt enable flag (IE) controls the entire interrupt process.

Interrupt Control Bits and Interrupt Processing: Locations $000 to $003 in RAM are reserved for the

interrupt control bits which can be accessed by RAM bit manipulation instructions.

The interrupt request flag (IF) cannot be set by software. MCU reset initializes the interrupt enable flag (IE)

and the IF to 0 and the interrupt mask (IM) to 1.

A block diagram of the interrupt control circuit is shown in figure 8, interrupt priorities and vector

addresses are listed in table 2, and interrupt processing conditions for the 7 interrupt sources are listed in

table 3.

HD404369F Scheda tecnica(PDF) 17 Page - Renesas Technology Corp